poly open cmp

**Poly Open CMP (POC) and Self-Aligned Gate Contact** is the **process module that exposes the top of polysilicon (or metal) gate stacks for electrical contact formation** — using a targeted CMP step to selectively remove the etch stop layer (SiN cap) only over gate structures while preserving it over active regions, enabling contacts to be formed directly on top of gate electrodes without requiring photolithography alignment, thus allowing tighter contact-to-gate pitch and denser layouts that directly improve circuit area efficiency. **Problem: Landed vs Self-Aligned Contact** - Traditional approach: Separate contact photomask → must align contact hole to gate → requires alignment margin → limits how close contacts can be to gate edge. - Layout constraint: Gate-contact separation must accommodate overlay error → "no-land contact" risk → limits cell size. - Self-aligned contact: Contact defined by SAC mask → contacts can land on gate + adjacent areas → alignment margin relaxed → denser layout. **Poly Open CMP (POC) Flow** 1. After gate stack patterning: Gate (poly or metal) capped with SiN hardmask cap. 2. Deposit ILD (inter-layer dielectric, typically SiO₂ or USG). 3. **POC CMP**: Polish ILD until SiN gate cap is exposed (visible) on field → SiN cap protrudes above field ILD. 4. Optional: Light etch of SiN cap → expose gate top surface. 5. Metal (W, Ru, Co) deposition → fills exposed gate top → contact formed directly on gate. 6. CMP → planarize metal → gate contact complete. **Selectivity Requirements** - POC CMP must stop on SiN (gate cap) while removing surrounding SiO₂ ILD. - Selectivity: SiO₂:SiN > 15:1 → SiO₂ polishes fast, SiN polishes slowly → controlled stop on SiN. - Slurry: Colloidal silica or ceria → ceria particles selectively attack SiO₂ vs SiN → high selectivity achievable. - Dishing risk: If selectivity not perfect → SiN cap also dished → gate top not cleanly exposed. **Self-Aligned Gate Contact (SAC)** - After POC, ILD and gate tops are coplanar or gate slightly raised. - Lithography defines contact openings over gate area → contact etch → SiN cap provides etch stop at gate top. - If contact slightly misaligned → SiN cap sidewalls prevent contact shorting to adjacent active area → self-aligned protection. **Contact Over Active Gate (COAG)** - Advanced self-aligned contact technology where contact is formed directly on top of gate in the active area. - Eliminates need for separate "middle contact" area → gate contact and S/D contacts at same level. - Enables: SRAM bit cell shrink → standard cell height reduction → library cell area compression. - Used at 7nm, 5nm, 3nm in different forms by Intel and TSMC. **Etch Stop Scheme** - SiN on gate top: Etch stop during contact etch. - SiON on active area: If different etch stop chemistry desired → two-material etch stop system. - Contact etch: High aspect ratio (AR 8–15:1) → very selective etch → C₄F₈/Ar chemistry → etch SiO₂, stop on SiN. **Impact on Standard Cell Design** - POC + SAC: Contact-to-gate space reduced from 20nm → 6nm effective → enables CPP (contacted poly pitch) reduction. - CPP: Gate pitch including contact landing area → POC reduces required gate pitch → denser transistor arrays. - TSMC N5: CPP = 51nm using POC + COAG vs older nodes needing > 70nm for same function. Poly open CMP and self-aligned gate contacts are **the lithographic workaround that enables sub-50nm contacted poly pitch by eliminating the overlay margin that would otherwise force wider gate spacing** — by using SiN gate caps as both hardmask during gate etch and self-aligned etch stop during contact etch, this process module converts the previously layout-limiting gate-to-contact alignment problem from a photolithography overlay challenge into a deposition thickness control challenge, delivering the cell area reduction needed for 5nm and 3nm standard cell libraries to fit the design complexity of modern AI accelerators and mobile SoC chips.