positive bias temperature instability (pbti)

PBTI (Positive Bias Temperature Instability) Overview PBTI is a reliability degradation mechanism in NMOS transistors with high-k/metal gate stacks where positive gate bias at elevated temperature causes threshold voltage to shift positive (increase), reducing drive current over the device lifetime. Mechanism 1. Positive Vgs applied to NMOS gate attracts electrons toward the high-k dielectric. 2. Electrons become trapped in pre-existing defects (oxygen vacancies) within the high-k layer (HfO₂). 3. Trapped negative charge in the dielectric shifts Vt positive (higher Vt = lower drive current). 4. Higher temperature accelerates trapping kinetics. PBTI vs. NBTI - PBTI: Affects NMOS under positive gate bias. Caused by electron trapping in high-k dielectric. Became significant with HfO₂ introduction at 45nm. - NBTI: Affects PMOS under negative gate bias. Caused by interface state generation at Si/SiO₂ interface. Has been a concern since 130nm. - Both: Vt shift increases with time, voltage, and temperature. Both must meet 10-year lifetime specs. Recovery - PBTI partially recovers when bias is removed (trapped electrons de-trap). - Recovery makes characterization tricky—measuring Vt shift after removing stress underestimates the true degradation. - Fast measurement techniques (< 1μs after stress removal) capture degradation before recovery. Mitigation - High-k Process Optimization: Reduce oxygen vacancy density through post-deposition annealing and composition tuning. - Interface Layer Engineering: Optimize SiO₂ interfacial layer thickness and quality. - Fluorine Incorporation: F passivates high-k defects, reducing available trap sites. - Voltage Guard-Banding: Design circuits to tolerate expected Vt shift over product lifetime. Testing - Accelerated stress at 125°C, 1.1-1.2× nominal Vdd. - Extrapolate Vt shift to 10-year lifetime using power-law time dependence (ΔVt ∝ t^n, n ≈ 0.15-0.25).