power analysis chip

**Power Analysis** — verifying that a chip's power delivery network provides stable voltage to all transistors under operating conditions. **IR Drop** - Voltage drops as current flows through resistive power grid - If local voltage drops too much, gates slow down and may fail timing - Static IR drop: Average current analysis - Dynamic IR drop: Transient current spikes (worst case — many gates switching simultaneously) - Target: < 5-10% supply voltage drop at any point **Electromigration Check** - Verify current density in all power wires is within safe limits - Excessive current → wire degradation over time (see EM reliability) **Power Estimation** - **Dynamic Power**: $P = \alpha C V^2 f$ (switching activity x capacitance x voltage$^2$ x frequency) - **Leakage Power**: Static current through off-state transistors. Significant at advanced nodes (30-50% of total) - **Short-circuit Power**: Brief current during switching transitions **Tools**: Synopsys PrimePower, Cadence Voltus, ANSYS RedHawk **Optimization** - Clock gating (reduce switching activity — biggest lever) - Multi-Vt cells (HVT on non-critical paths reduces leakage) - Power gating (shut down unused blocks completely) - Voltage scaling (lower V for power-constrained modes) **Power analysis** is critical — modern chips are often power-limited before they are area-limited.