power delivery network

**Power Delivery Network (PDN) Design** is the **hierarchical power distribution from source to load — optimizing capacitive decoupling at multiple levels (on-chip MOSCAPs, package caps, board caps) — achieving target impedance Ztarget = Vdroop / Idelta — ensuring supply voltage remains within ±5% despite transient current demand — essential for reliable operation and preventing voltage collapse**. PDN is a critical design concern. **Target Impedance Method** Target impedance is determined from allowable voltage droop: Ztarget = Vdroop / Idelta, where Vdroop is maximum tolerable voltage drop (typically ±5% of Vdd, e.g., 50 mV for 1.0 V supply), and Idelta is maximum current transient (e.g., 10 A for logic block). Example: Ztarget = 50 mV / 10 A = 5 mΩ. PDN impedance (vs frequency) must be 10 pF on-chip decap), (2) package impedance target ~2-3 mΩ at 100 MHz, (3) board impedance target ~2-3 mΩ at 10 MHz. Allocation depends on current spectrum and design priorities. **On-Chip PDN (Power Straps and Substrate Injection)** On-chip PDN includes: (1) power straps (M1-M9/M10 mesh of power/ground lines), (2) MOSCAPs and well-caps interspersed. Power strap inductance is minimized via: (1) fine pitch (reduce path length for return current), (2) multiple parallel vias (reduce via inductance), (3) interlocking mesh (current can flow in shortest path). Substrate injection (using substrate as return path for local current) reduces strap inductance but couples noise into substrate (analog blocks affected). Modern designs balance: use straps for digital (power/ground return), substrate tap carefully placed in digital, analog isolated via DNW. **VRM Bandwidth Limitation** Voltage regulator module (VRM, on-board) controls supply voltage via feedback control. VRM has bandwidth limit (~10 MHz typical, design-dependent): (1) below bandwidth, VRM actively regulates (maintains voltage), (2) above bandwidth, VRM is passive (cannot respond fast enough, impedance determined by internal L and C). PDN design must decouple transient currents at frequencies above VRM bandwidth (via on-die and package capacitors). If transient contains significant energy above VRM bandwidth, on-die/package caps must handle it alone. **PDN Simulation (S-Parameters + SPICE)** PDN simulation: (1) extract or measure S-parameters (impedance vs frequency) for each component (cap, strap, via, board), (2) construct equivalent circuit (model as series and parallel RLC elements, with S-parameter models for frequency-dependent behavior), (3) simulate voltage response to transient current (via SPICE or circuit simulator), (4) check if voltage drop stays