power gating
**Power Gating** — completely shutting off supply voltage to unused chip blocks by inserting sleep transistors between the block and the power rail, eliminating both dynamic and leakage power.
**How It Works**
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- Sleep transistors are large PMOS (header) or NMOS (footer) devices
- When active: Sleep transistors ON → full VDD to logic
- When gated: Sleep transistors OFF → logic disconnected from power
**Power Savings**
- Eliminates leakage entirely in powered-off blocks
- At 5nm: Leakage can be 30-50% of total power → huge savings
- Example: Mobile SoC powers off GPU cores when not rendering
**Implementation Challenges**
- **Retention**: Flip-flop state is lost when power is off. Retention flip-flops (balloon latch) save critical state
- **Isolation**: Outputs of powered-off block must be clamped to valid levels (isolation cells)
- **Rush current**: Turning block back on causes large inrush current → power-up sequence needed
- **Always-on logic**: Some control logic must remain powered (wake-up controller)
**Power Intent (UPF/CPF)**
- IEEE 1801 UPF (Unified Power Format) describes power domains, isolation, retention in a standardized format
- EDA tools use UPF to automatically insert power management cells
**Power gating** is the most effective leakage reduction technique — essential for any battery-powered or thermally-constrained chip.