Power Gating

**Power Gating and MTCMOS Design** is **a sophisticated dynamic power management technique where entire circuit blocks are switched between active and standby power domains using high-threshold-voltage (HVT) switch transistors — enabling dramatic reductions in standby leakage current and chip power consumption**. Power gating addresses the fundamental challenge that modern semiconductor devices consume substantial power even when not performing useful computations, due to subthreshold and gate leakage currents in transistors with reduced threshold voltages optimized for performance. The multi-threshold CMOS (MTCMOS) approach uses multiple threshold voltage device options, with low-threshold-voltage (LVT) transistors for performance-critical logic providing superior switching speed and drive current, while high-threshold-voltage (HVT) transistors are employed for power switches and non-critical paths. The power gating switches consist of high-threshold-voltage transistors carefully designed to conduct the peak current of the powered-down block while minimizing voltage drop during active operation, and completely blocking leakage current in off-state operation. The header switch connects the power supply to the switched power domain, while the footer switch connects the switched ground to circuit ground, with both switches optimized for minimal area and resistance while maintaining reliable switching behavior. The switch sizing for power gates requires careful analysis of transient current surges during power-up transitions, where the rapid transition from off-state to on-state can cause large dV/dt effects and voltage droop if switch resistance is not carefully managed. The control circuitry for power gates must carefully sequence power-up and power-down transitions to avoid current inrush surges that could exceed power delivery network capacity, typically employing gradual ramp-up of power switch gates rather than abrupt switching. State retention elements (flip-flops, latches) in power-gated domains must be designed to retain logic state even when power is removed, using special retention structures powered by always-on supplies to prevent loss of critical state information. **Power gating and MTCMOS design enable dramatic reductions in standby power consumption through selective disabling of non-essential circuit blocks.**