power gating design
**Power Gating** implements **circuits to completely shut off supply voltage to idle blocks, reducing leakage to near zero**, using MTCMOS power switches with retention elements and isolation cells.
**Why Power Gating**: At sub-20nm FinFET, leakage can equal dynamic power. A block consuming 100mW idle leakage reduces to <1mW with gating. For mobile SoCs (cores 90%+ idle), saves 40-60% total power.
**Power Switch Design**:
| Parameter | Header (PMOS) | Footer (NMOS) |
|-----------|-------------|---------------|
| Placement | Above cell rows | Below cell rows |
| Advantage | No ground bounce | Smaller (higher mobility) |
| Disadvantage | Larger PMOS | Ground bounce risk |
Sizing determines: **Ron** (must keep IR drop <10mV at peak current), **area** (5-10% of gated block), **rush current** (inrush during power-on — daisy-chain turn-on limits this).
**Retention Strategy**: **Retention flip-flops** — dual-rail FFs with balloon latch on always-on supply, 30-50% larger than standard FF; **Save to SRAM** — firmware saves state before shutdown, slower but less area; **UPF specification** defines retention requirements.
**Isolation Cells**: Powered-down block outputs clamped to known value. AND-based (clamp 0), OR-based (clamp 1), latch-based (hold last value). Placed at power domain boundaries.
**Implementation Flow**: Architecture (define domains in UPF) -> Synthesis (insert isolation, retention, level shifters) -> Floorplan (power switch rings, virtual rail routing) -> P&R (route virtual VDD/VSS, verify IR drop) -> Verification (power state coverage, isolation assertion, rush current) -> Signoff (power-aware STA with switch Ron, EM analysis).
**Power gating achieves what no amount of clock gating or voltage scaling can: zero dynamic and near-zero leakage for idle blocks — the essential enabler of modern mobile battery life.**