power intent

**Power intent** is the formal specification of a chip's **power architecture** — defining all power domains, voltage levels, power switches, isolation requirements, retention strategy, level shifters, and power state transitions in a structured, machine-readable format that drives the entire low-power design and verification flow. **What Power Intent Specifies** - **Power Domains**: Which logic blocks belong to which power domain — each domain has its own supply voltage and power management capability. - **Supply Networks**: The VDD and VSS connections for each domain — real (always-on) vs. virtual (switchable) supplies. - **Power States**: The set of valid power modes the chip can be in — e.g., all-on, core-off, deep-sleep, hibernate — and the allowed transitions between them. - **Power Switches**: Which domains can be gated, what switch cells to use, and the control signals. - **Isolation**: At each domain boundary, the type of isolation (clamp-0, clamp-1, latch), the isolation control signal, and which direction (input/output) requires isolation. - **Retention**: Which flip-flops in a switched domain need retention, the save/restore control signals, and the retention cell type. - **Level Shifters**: Where voltage level conversion is needed between domains at different voltages — the type and location of level shifter cells. - **Power Sequencing**: The order in which domains are powered up/down, when isolation and retention signals are asserted/de-asserted. **Why Power Intent Is Needed** - Modern SoCs have **10–50+ power domains** with complex interactions — manually tracking all requirements is error-prone and unscalable. - Power intent provides a **single source of truth** that all EDA tools consume: - **Synthesis**: Inserts isolation cells, level shifters, retention flops. - **Place and Route**: Places power switches, routes multiple supply networks, places special cells at domain boundaries. - **Verification**: Checks that all power intent rules are correctly implemented — no missing isolation, correct level shifting, proper sequencing. - **Simulation**: Power-aware simulation models domain shutdowns and their effects on functionality. **Power Intent Formats** - **UPF (Unified Power Format)**: IEEE 1801 standard. Industry-standard, supported by all major EDA vendors. Synopsys-originated. - **CPF (Common Power Format)**: Si2/Cadence format. Alternative to UPF, primarily used in Cadence flows. - Both specify the same concepts — power domains, switches, isolation, retention, level shifters — in different syntax. **Power Intent in the Design Flow** 1. **Architecture**: Architect defines the power domain structure and power states. 2. **UPF/CPF Authoring**: Write the power intent file describing all domains and requirements. 3. **Synthesis**: Tool reads UPF/CPF, inserts special cells, implements power structure. 4. **P&R**: Physical implementation with power switches, dual-rail routing, special cell placement. 5. **Verification**: Power-aware simulation and formal checks validate correctness. 6. **Sign-Off**: Final power integrity and low-power verification. Power intent is the **blueprint of low-power design** — it transforms the power architect's vision into a precise, verifiable specification that drives every step of the implementation flow.