Power on Reset

Power-on reset is the circuit that holds an entire chip in a known, safe state until its own supply voltage has actually risen high enough for the rest of the logic to work correctly — solving a chicken-and-egg problem every chip faces at startup, since a reset signal generated by ordinary digital logic cannot be trusted until that same logic has a stable, fully-arrived supply to run on, which is exactly the condition the chip has not reached yet the instant power is first applied.

The circuit works by comparing the rising supply voltage against a threshold and holding every flip-flop and latch on the chip in a defined reset state until that threshold is crossed. As VDD ramps up from zero, internal nodes throughout the chip are in genuinely unpredictable states — registers can power up holding random values, state machines can wake into illegal states, and any logic that depends on a stable supply voltage to function correctly simply has no guarantee of correct behavior yet. The power-on reset circuit's entire job is to recognize when the supply has risen enough that the rest of the chip's circuitry can be trusted, and only then release the reset signal that lets normal operation begin — everything downstream of that release assumes a stable, sufficient supply, and the POR circuit is what actually verifies that assumption before anything else gets to rely on it.

This creates a genuine bootstrapping problem, because the power-on reset circuit itself has to function correctly using the exact supply voltage it is still in the process of evaluating. Ordinary digital logic assumes a full-swing, stable supply rail to operate reliably — exactly the condition that does not yet exist during the window a POR circuit has to monitor. This is why power-on reset circuits are built from simple, robust analog building blocks specifically chosen to function across the widest possible range of partially-ramped supply voltages, rather than from digital logic that would itself need the very reset signal it's supposed to be generating.

The threshold itself can be set two fundamentally different ways, and the choice trades precision against how early in the power-up sequence the circuit can actually run. A simple resistor-divider threshold compares a fraction of VDD against a fixed reference and works at very low supply voltages, often low enough to be useful almost from the first instant power is applied, but the threshold it produces drifts with temperature and process variation, which is acceptable for a coarse, early-stage reset but not precise enough for applications that need a tightly specified trip voltage. A bandgap-referenced threshold delivers the precise, temperature-stable trip point this series has already covered in detail — but a bandgap reference needs its own startup circuit and a certain minimum supply voltage before it produces a valid, stable reference at all, which means the precision threshold cannot be the very first thing evaluated during power-up; something simpler usually has to get the chip far enough along first.

This is why many real power-up sequences use a coarse detector to bootstrap a precision one, rather than relying on bandgap precision from the very first instant. A simple, crude threshold circuit can release an early, conservative reset state that is good enough to let the bandgap reference's own startup circuit begin operating safely; once that reference has stabilized, a second, more precise comparison against the bandgap-derived threshold can take over for any downstream circuit — a brown-out detector or undervoltage lockout — that genuinely needs the tighter trip-point accuracy. Power-on reset and bandgap-reference startup are, in this sense, solving each other's chicken-and-egg problem in sequence rather than either one working in isolation.

Power-on reset is frequently confused with, but functionally distinct from, brown-out detection and undervoltage lockout, which monitor the supply continuously rather than only once at startup. Power-on reset handles exactly one event: the initial transition from no power to adequate power, after which its job is essentially done until the next full power cycle. Brown-out detection and undervoltage lockout instead continuously monitor the supply during normal operation, ready to trigger a reset or shutdown if VDD droops below a safe level mid-operation — a supply glitch, a battery nearing depletion, a transient load spike — a genuinely different failure mode than the one-time startup transient power-on reset exists to handle, even though both ultimately compare a supply voltage against a threshold and both often share circuit blocks, including the same bandgap reference, to do it.

Power-on reset is the first circuit on a chip that has to work, functioning correctly before the supply it depends on has even finished arriving — every other circuit this series has covered, from a charge pump generating its own boosted rail to a bandgap reference settling to its precision output, implicitly depends on power-on reset having already done its job and released the chip into a known, valid starting state. It is the specific answer to the narrowest possible version of the bootstrapping problem every power-up sequence faces: something has to go first, with nothing yet guaranteed to be stable, and power-on reset is built to be exactly that something.