Power Sequencing

Power sequencing is the discipline of controlling the order and timing in which a chip's multiple supply rails come up, and it exists because getting that order wrong can damage silicon even when every individual rail's own power-on reset is working flawlessly. A modern SoC rarely runs on one supply — core logic, I/O, memory, and analog blocks each typically need their own rail, often at different voltages, and bringing those rails up in the wrong relative order is a fundamentally different, often more severe failure mode than any single rail's own startup transient.

The classic failure case is a core rail powering up after, rather than before, an I/O rail that's already driving signals into the chip. Every I/O pin on a chip carries electrostatic discharge protection diodes connecting it to the internal power rails, there specifically to shunt dangerous voltage spikes safely away during handling — but those same diodes assume the internal rail they connect to is actually powered. If an external signal drives an I/O pin to a valid logic level while the core rail behind it is still at zero volts, the protection diode between that pin and the unpowered core rail can forward-bias, conducting uncontrolled current from the external signal source directly into a rail that has no supply behind it to absorb it. This is not a logic error the chip can simply reset its way out of — forward-biasing a protection diode this way is a real electrical stress event, capable of triggering latch-up or causing permanent damage, depending on how much current flows and for how long.

This is precisely why power sequencing has to be coordinated through an explicit handshake between rails, rather than left to each regulator's own independent timing. Each voltage regulator in a sequenced power tree asserts its own power-good signal only once its own output has crossed its threshold and stabilized — a condition stricter than simply crossing a level once, since a regulator's output can ring or overshoot briefly during its own turn-on transient. That power-good signal then gates the enable input of the next regulator in the sequence, so the second rail is physically prevented from beginning to ramp until the first rail has proven itself stable, cascading through as many rails as the system actually has, with the final rail's power-good typically the signal that finally releases the chip's own power-on reset.

Power sequencing and the power-on reset already covered in this series operate at genuinely different layers of the same problem, not as redundant checks of the same thing. Power-on reset verifies that one specific rail has reached a valid voltage before releasing the logic that depends on it — a per-rail concern, solved entirely within that one supply's own startup circuit. Power sequencing instead coordinates the relative timing between multiple rails, a system-level concern that exists precisely because a chip can have every individual rail's power-on reset working correctly and still suffer the exact damage sequencing exists to prevent, if those perfectly functional rails simply arrive in the wrong relative order.

Power-down sequencing matters for the identical reason, in reverse, and is frequently the half of the problem a design overlooks. The same forward-biased-diode risk that threatens a chip during power-up threatens it again during power-down if rails are cut in the wrong order — an I/O rail disappearing while the core rail it protects is still powered, or vice versa, can forward-bias the identical protection diodes from the opposite direction. A complete power sequencing specification therefore defines both a power-up order and a power-down order, and the two are not always simply the reverse of each other, since some chips tolerate a faster or differently-ordered shutdown than their required power-up sequence allows.

Modern power management ICs implement sequencing directly in hardware or configurable firmware specifically because getting this right by board-level timing alone is fragile. A system relying on component tolerances and PCB trace delays to achieve correct relative timing between rails is gambling against manufacturing variation, temperature, and load-dependent regulator response time — any of which can shift one rail's actual ramp time enough to violate the required ordering even when the nominal design looked correct on paper. Dedicated sequencing hardware instead enforces the order explicitly through the power-good handshake chain, making the correct sequence a logical guarantee rather than a timing coincidence the board layout happens to produce.

Power sequencing is the system-level layer this series' power-management thread has been building toward — power-on reset and brown-out detection each guard one rail in isolation, but neither one can catch a failure that only exists in the relationship between rails arriving in the wrong order. A chip with flawless per-rail protection circuits can still be damaged on its very first power-up if nothing coordinates when each of those rails is actually allowed to begin ramping, which is exactly the gap power sequencing is built to close.