power switch cell

**A power switch cell** (also called a **header switch** or **footer switch**) is a specialized standard cell containing a **large power-gating transistor** that connects or disconnects a power domain from its supply rail — enabling entire blocks of logic to be completely powered down during idle periods to eliminate leakage power. **Why Power Switching?** - At advanced nodes, **leakage power** can be 30–50% of total power — transistors leak current even when not switching. - Clock gating saves dynamic power but does nothing for leakage — the transistors remain powered and leaking. - **Power gating** (shutting off the supply voltage) is the only way to reduce leakage to near zero. - Power switches are the physical mechanism that implements power gating. **How Power Switches Work** - **Header Switch**: A large PMOS transistor between VDD and the local power rail (virtual VDD, or VVDD). When the switch is on, VVDD ≈ VDD. When off, VVDD floats to ground — all logic in the domain loses power. - **Footer Switch**: A large NMOS transistor between the local ground (virtual VSS, or VVSS) and VSS. When off, VVSS floats toward VDD. - **Header switches** are more common in modern designs — PMOS switches between VDD and virtual VDD. **Power Switch Cell Design** - **Large Transistor**: The switch transistor must be large enough to carry the entire block's current with minimal voltage drop ($IR$ drop across the switch). - **Low Ron**: The switch's on-resistance must be small — typically <50–100 mΩ to keep the voltage drop under 20–50 mV. - **Cell Array**: A single switch cell is not large enough for a whole block. Many switch cells are placed in a row/column forming a **switch array** — all controlled by the same enable signal. - **Daisy Chain Control**: Switch cells may be turned on sequentially (daisy chain) rather than simultaneously to limit **inrush current** during power-up. **Power-Up Sequence** 1. **Sleep State**: Switch off — VVDD = 0V, all logic in dormant state, leakage near zero. 2. **Power-Up Signal**: Enable signal activates switch cells (may be staggered via daisy chain). 3. **Ramp-Up**: VVDD ramps from 0 to VDD — supply stabilizes. 4. **Isolation Release**: Isolation cells release, allowing signals from the powered domain to drive outputs. 5. **State Restore**: Retention flip-flops restore their saved state. 6. **Normal Operation**: Block resumes full function. **Design Considerations** - **IR Drop**: The switch adds resistance in the supply path — must be sized to meet IR drop budget under worst-case current draw. - **Inrush Current**: When switching on, the block's decoupling capacitance charges rapidly — creating a current spike. Staggered turn-on mitigates this. - **Always-On Logic**: Some cells (retention FFs, isolation cells, control logic) must remain powered — connected to the real (not virtual) VDD. - **Physical Planning**: Switch cells must be distributed across the power domain — typically in a ring or grid pattern for uniform IR drop. Power switch cells are the **enabling technology** for power gating — they transform leakage power from an unavoidable cost into an engineering choice, providing near-zero leakage for any block that can tolerate being powered down.