rapid thermal processing rtp

**Rapid Thermal Processing (RTP) and Advanced Annealing** is the **family of high-temperature, short-duration heat treatment techniques used to activate dopants, densify films, and repair crystal damage in CMOS fabrication — progressing from conventional furnace annealing (minutes at 800-1000°C) to spike annealing (seconds at 1000-1100°C) to millisecond flash/laser annealing (sub-ms at 1100-1400°C) as each new technology node demands higher dopant activation with less thermal diffusion, tightening the thermal budget that constrains every high-temperature step in the process flow**. **The Thermal Budget Problem** Every high-temperature step causes dopant diffusion: - Diffusion length: L = √(D × t), where D is diffusivity (exponentially dependent on temperature) and t is time. - A 1000°C, 10-second spike anneal diffuses boron ~3 nm — acceptable at 14 nm node but too much at 3 nm where junction depth targets are ~5 nm. - Solution: increase temperature (more activation) while decreasing time (less diffusion). This drives the evolution toward ultra-short annealing. **Annealing Technology Evolution** **Furnace Anneal (Legacy)** - Temperature: 800-1000°C. Duration: 10-60 minutes. Ramp rate: 5-20°C/min. - Uniform, batch processing. Excessive thermal budget for modern devices. - Still used for: STI liner oxidation, LPCVD film densification. **Spike RTP** - Temperature: 1000-1100°C. Dwell time at peak: 1-2 seconds. Ramp rate: 100-250°C/sec. - Lamp-heated single-wafer chamber. Rapid heating minimizes diffusion. - Primary use: S/D dopant activation at 14 nm+. - Dopant activation: ~70-80% of implanted dose. **Flash Lamp Anneal** - Temperature: 1100-1350°C (wafer surface). Duration: 0.1-20 ms. - Xenon flash lamps heat only the top ~10-50 μm of the wafer. Bulk substrate stays at 500-800°C (pre-heated), acting as a heat sink. - Activation: >90% at 1300°C. Diffusion: <1 nm. - Used at 7 nm and below for NMOS S/D activation (Si:P requires high-T for activation). **Laser Anneal** - **Pulsed Laser (Nanosecond)**: Excimer laser (308 nm) or green laser (532 nm). Melts or near-melts the top 50-200 nm. Duration: 20-200 ns. Used for S/D activation with near-zero diffusion. - **Scanned CW Laser (Microsecond)**: CO₂ laser scanned across the wafer. Each point heated for ~100-500 μs. Temperature: 1100-1300°C. Used for silicide formation and S/D activation. - **Sub-melt laser anneal**: Heat to just below Si melting (1414°C) for maximum activation without amorphization artifacts. **GAA-Specific Thermal Challenges** In gate-all-around nanosheet fabrication: - SiGe sacrificial layers must not interdiffuse with Si channel layers. Thermal budget must keep Ge diffusion <0.5 nm. - S/D epitaxy temperatures (550-700°C) are relatively benign. - Post-epi activation anneal must activate B/P in S/D without diffusing Ge across the SiGe/Si interface. - Millisecond anneal is essential at GAA nodes. **Backside BSPDN Thermal Constraints** With backside power delivery, the front-side BEOL (Cu interconnects, low-k dielectrics) is completed before backside processing. All backside steps must stay below 400°C — the Cu/low-k thermal limit. This forces low-temperature backside dielectric, metal deposition, and bonding processes. RTP and Advanced Annealing are **the thermal precision tools that activate dopants without destroying the nanometer-scale junctions and interfaces of modern transistors** — the ongoing engineering race to deliver enough thermal energy for dopant activation in ever-shorter time windows, pushing toward the fundamental limits of how fast silicon can be heated and cooled.