razor flip-flops

**Razor flip-flops** are the **timing-speculative storage elements that compare main-latch data with delayed shadow sampling to detect late-arrival timing errors** - they are a foundational circuit for near-threshold and better-than-worst-case operation. **What Are Razor Flip-Flops?** - **Definition**: Sequential elements augmented with shadow capture and mismatch detection logic. - **Detection Principle**: If main and shadow samples disagree, a timing violation is flagged. - **System Integration**: Error signal triggers replay, stall, or local correction control. - **Design Constraints**: Careful hold-time management and metastability-aware implementation. **Why They Matter** - **Voltage Scaling Enablement**: Supports operation below conservative static timing limits. - **Adaptive Robustness**: Real-time error feedback reflects actual silicon and workload conditions. - **Energy Efficiency**: Reduces fixed guardband overhead in nominal operation. - **Yield Extension**: Weak but correctable silicon can remain in productive use. - **Research to Product Path**: Proven concept for resilient CPU and accelerator pipelines. **How Engineers Deploy Razor** - **Path Selection**: Insert Razor where timing sensitivity and payoff are highest. - **Recovery Design**: Build low-latency replay mechanism with bounded throughput penalty. - **Calibration and Validation**: Characterize error behavior across PVT and tune control thresholds. Razor flip-flops are **a key circuit primitive for runtime timing resilience** - by converting silent late paths into visible recoverable events, they unlock aggressive efficiency operating points.