Refresh Cycle
A refresh cycle is the periodic operation that rereads and rewrites every cell in a dynamic RAM to prevent the stored data from fading away, and it is the defining maintenance requirement that makes DRAM "dynamic." Because a DRAM cell holds its bit as a small electrical charge on a capacitor, and that charge slowly leaks away through unavoidable paths, the data would be lost within a short time if nothing intervened. The refresh cycle is that intervention: on a regular schedule, the memory reads each row of cells and writes the sensed values back, replenishing the charge before it decays past the point of reliable detection.
Refresh is the fundamental trade that buys DRAM its density and low cost, which is why the requirement is accepted rather than engineered away. A dynamic cell uses roughly one transistor and one capacitor per bit, far fewer components than a static memory cell, which is why DRAM is dense and cheap. The price of that simplicity is that the cell cannot hold its value indefinitely on its own and must be refreshed. So refresh is not a defect but the direct consequence of the design choice that makes DRAM attractive in the first place — the memory accepts an ongoing maintenance obligation in exchange for storing far more bits per unit of silicon.
A refresh operation works by exploiting the fact that reading a DRAM row already restores it, so refreshing is essentially reading every row on a schedule. When a row is activated and its cells are sensed, the sense amplifiers drive each bit line to a full logic level and write that value back into the cells, which replenishes their charge. A refresh cycle takes advantage of this by stepping through all the rows of the array within a required time window, activating each one so its contents get sensed and rewritten. The entire memory stays valid as long as every row is visited often enough that no cell's charge decays past the point where the sense amplifier can still tell a one from a zero.
Refresh imposes real costs on a system beyond the memory chip itself, which is part of why it is an important design consideration rather than an invisible detail. The memory must spend some of its time doing refresh rather than serving reads and writes, and a memory controller must orchestrate the refresh schedule, ensuring every row is covered within the allowed interval while interleaving refresh with normal access. This adds complexity and consumes a fraction of the memory's bandwidth and power. Static memory, which needs no refresh, avoids these costs but at the expense of much lower density and higher cost, so the refresh burden is the practical boundary between where designers choose dynamic versus static memory.
The refresh requirement also connects memory behavior to data retention time and to power, which matters especially for low-power and standby operation. How often refresh must happen depends on how quickly the cells leak, which varies with temperature and process, so hotter conditions generally demand more frequent refresh. In battery-powered devices, refresh is a continuous background power draw even when the memory is otherwise idle, which is why low-power memory designs pay close attention to minimizing refresh overhead. The refresh cycle is thus not only about correctness but about the energy cost of simply keeping data alive.
Read the refresh cycle as the upkeep DRAM pays for being cheap and dense: a continuous, row-by-row reread-and-rewrite that replenishes the leaking charge in every cell, the defining chore of dynamic memory and the dividing line between it and the costlier static memory that needs no such maintenance.