retention flop

**A retention flip-flop (retention flop)** is a special sequential cell that **saves its stored value** before the power domain is shut down and **restores it** when power returns — enabling the logic block to resume operation exactly where it left off without requiring re-initialization. **Why Retention Is Needed** - Power gating completely removes the supply voltage — all standard flip-flops lose their state (the stored 1s and 0s disappear). - Without retention, after power-up the block must be **fully re-initialized**: reset, reconfigured, and re-loaded with data. This takes time and energy, negating some of the power savings. - Retention flip-flops allow **fast wake-up**: save state before shutdown, restore state after power-up, and immediately resume — reducing wake-up latency from microseconds to nanoseconds. **Retention Flip-Flop Architecture** - **Main Flip-Flop (Switchable)**: Standard flip-flop connected to the virtual VDD (VVDD) — powered down during sleep. - **Shadow Latch (Always-On)**: A small, low-power latch connected to the always-on VDD (real VDD) — remains powered during sleep to retain the state. - **Save Signal**: Before power-down, the save signal copies the main FF's value to the shadow latch. - **Restore Signal**: After power-up, the restore signal copies the shadow latch's value back to the main FF. **Operation Sequence** 1. **Normal Operation**: Main FF operates normally. Shadow latch is dormant. 2. **Save**: Assert SAVE — data from main FF is copied to shadow latch. 3. **Power Down**: Switches turn off — main FF loses power, shadow latch retains the value on always-on supply. 4. **Power Up**: Switches turn on — main FF powers up in an unknown state. 5. **Restore**: Assert RESTORE — shadow latch value is copied back to main FF. State is restored. 6. **Resume**: Normal operation continues from the preserved state. **Retention Flop Types** - **Balloon Latch**: Uses a high-Vth (low-leakage) latch as the shadow element — minimizes leakage during retention. - **Master-Shadow**: The shadow latch is a separate master latch with always-on supply. - **Retention with Reset**: Some retention flops support both retention and asynchronous reset — providing flexibility in the wake-up sequence. **Design Tradeoffs** - **Area**: Retention flops are **30–60%** larger than standard flip-flops — the shadow latch and additional control logic add overhead. - **Power**: Small additional leakage from the always-on shadow latch. But this is much less than the leakage of keeping the entire block powered on. - **Timing**: The save and restore operations add to the power-down and power-up latency — but are much faster than full state re-initialization. - **Selective Retention**: Not all flip-flops need retention — only those whose state is expensive to recompute. The designer selects which FFs get retention to minimize area overhead. **Physical Design** - Retention flops have **two power pins**: VVDD (switchable) and VDD (always-on). Physical design must route both power networks. - Placed within the switchable power domain but connected to both supply networks. Retention flip-flops are **essential for efficient power gating** — they bridge the gap between complete shutdown (maximum power savings) and instant resume (minimum wake-up overhead), making aggressive power management practical.