Ripple Voltage
# Ripple Voltage in Power Delivery
Ripple voltage is the AC component of a regulated power supply output — the oscillation around the nominal DC level that arises from imperfect filtering of the switching action in a buck converter, or from high-frequency noise coupled back from the load. A buck converter switching at 1 MHz, for example, creates a 1 MHz square-wave switching current in its inductor; that current flowing through the output impedance of the power stage produces a voltage wobble synchronized to the switching frequency. Ripple is separate from DC offset or thermal drift (IR drop); it is the high-frequency noise that occurs *at* the nominal voltage, and it matters because digital logic timing margins shrink when the supply voltage has sudden dips or spikes.
Ripple voltage and its complement, ripple current, are usually specified as peak-to-peak values in millivolts or milliamps. A 1.2 V supply with 50 mV ripple swings from 1.175 V to 1.225 V at the switching frequency. This is not a problem if the timing margin is large — a circuit designed for 1.0–1.4 V can tolerate ±2–3%. But at advanced nodes, where margin is already tight and clock frequencies are high, ripple can be a limiting constraint. A 50 mV ripple on a 0.9 V supply is already ±2.8%, leaving almost no room for process variation or temperature droop on top of it.
The physical sources of ripple are straightforward: a buck converter (or similar switched-mode power supply) creates a ripple current in its inductor because the switch alternates between on and off. During the on phase, the inductor current ramps up linearly. During the off phase, it ramps down. The output capacitor is supposed to absorb the ripple current and maintain a constant voltage, but no capacitor is ideal — it has equivalent series resistance (ESR) and equivalent series inductance (ESL), both of which translate ripple current into ripple voltage. A 10 µF ceramic capacitor with 50 mΩ ESR carrying a 1 A peak-to-peak ripple current generates 50 mV of ripple directly across its resistance, *before* any other impedances in the path.
Modern chip design manages ripple through hierarchy: bulk capacitance on the PCB (bulk caps are large, low-cost, but slow to respond due to PCB parasitics), mid-frequency ceramic capacitors closer to the package, and on-die decoupling capacitors that can respond to nanosecond-scale transients. The total is typically a mix: 50% bulk (large, slow), 30% intermediate, 20% on-die (small, fast). Each level has its own bandwidth and impedance profile, and the total impedance is the parallel combination of all of them — a hill-shaped curve that typically bottoms out in the 10 MHz range, where neither bulk nor on-die caps dominate.
Ripple voltage matters because digital logic timing is exponentially sensitive to supply voltage at advanced nodes. A 7 nm chip might see a 3–4% delay increase per 100 mV of supply droop, and a 50 mV ripple swing is enough to move the entire design from timing-safe to timing-marginal. Unlike IR drop (which is steady-state and gets modeled into the static timing analyzer), ripple couples directly to high-frequency switching noise in the logic — it becomes a jitter source and a timing-margin eroder. This is why power delivery design, once a secondary concern in older nodes, has become a first-class design constraint: ripple budget is now part of the electrical specification fed back to the voltage regulator team and the physical design team as a hard limit.
| Ripple source | Typical amplitude | Frequency | Mitigation |
|---|---|---|---|
| Output capacitor ESR | 20–100 mV | f_sw (1–10 MHz) | Lower ESR caps, parallel many caps |
| Output capacitor ESL | 10–50 mV | higher (10–100 MHz) | Via stitching, short traces, on-die caps |
| PCB trace inductance | 5–20 mV | f_sw and harmonics | Multiple vias, wider metal, shorter path |
| On-chip supply noise | 10–30 mV | logic switching (100+ MHz) | On-die decaps, localized return paths |
The distinction between ripple and droop is important operationally: ripple is cyclic and happens at a predictable frequency (the switching frequency), while droop is a slower, monotonic sag that happens on load transients. A timing analyzer might model droop as a static guardband (worst-case voltage ever seen), but ripple requires actual time-domain simulation because logic paths have different sensitivities depending on their phase relationship with the ripple cycle. A path that happens to sample its supply at the voltage peak sees less delay than one that samples at the trough — an effect called "supply-noise-induced timing variation" that becomes statistically significant at small geometries.