Risc
RISC, reduced instruction set computer, is a processor design philosophy that favors a small set of simple, fast, uniform instructions over a large set of complex ones, on the principle that a streamlined instruction set can be executed more quickly and pipelined more easily, yielding higher performance. It arose in the late 1970s and early 1980s as a deliberate counter-approach to the then-prevailing complex instruction set designs, and it reshaped processor architecture profoundly, influencing nearly all subsequent designs. RISC matters because its core insight — that simplicity in the instruction set enables speed in the hardware — proved broadly correct and durable.
The central RISC idea is that a small set of simple, uniform instructions can be made to execute very fast and to pipeline efficiently, whereas complex instructions are harder to speed up. Complex instruction set designs offered many elaborate instructions, some performing intricate multi-step operations, on the theory that this made programming and compilers' jobs easier. RISC argued the opposite: that most of those complex instructions were used rarely, that implementing them slowed the hardware, and that a lean set of simple instructions, each doing a small well-defined task, could be executed in a streamlined pipeline at high speed. Simplicity in the instruction set, in this view, buys speed in the implementation.
RISC designs share characteristic features: simple fixed-format instructions, a load/store model that accesses memory only through specific instructions, and a large register set to keep operands on-chip. Fixed, regular instruction formats are easy to decode quickly and to feed through a pipeline. The load/store model keeps memory access confined to dedicated load and store instructions while all computation happens between registers, which simplifies the pipeline. And a generous set of registers lets the processor keep many values close at hand, reducing slow memory traffic. These features work together to make the simple instructions execute rapidly in an efficient pipeline, which is the practical embodiment of the RISC philosophy.
RISC spawned a family of influential architectures, including MIPS, SPARC, and ARM, each applying the philosophy to great effect in different domains. The RISC approach was realized in several concrete instruction-set architectures that became important in their own right, serving workstations, servers, and eventually the enormous market of mobile and embedded devices. The breadth of successful RISC architectures demonstrated that the philosophy was not tied to one implementation but was a general and powerful approach, and these architectures carried RISC ideas into a wide range of computing, from high-performance machines to the processors in billions of phones.
RISC's deepest significance is that its core insight influenced nearly all later processor design, including processors that retained complex instruction sets. Even architectures that kept a complex instruction set for compatibility reasons came to use RISC-like techniques internally, translating complex instructions into simpler internal operations that could be executed in a streamlined, pipelined fashion. In this way the RISC philosophy permeated the whole field, shaping how processors are built even where the external instruction set remained complex. RISC thus represents not just a set of architectures but a durable idea about the relationship between instruction-set simplicity and hardware speed that reshaped the discipline.
Read RISC as the argument that simple is fast: a design philosophy favoring a small set of uniform, easily-pipelined instructions with a load/store model and many registers, realized in architectures like MIPS, SPARC, and ARM, whose core insight — that instruction-set simplicity buys hardware speed — came to influence essentially all later processor design.