rocm amd gpu hip
**HIP/ROCm AMD GPU Programming: CUDA Portability and MI300X — enabling GPU-agnostic code and AMD CDNA acceleration**
HIP (Heterogeneous Interface for Portability) enables single-source GPU code compiling to both NVIDIA (via CUDA) and AMD (via HIP runtime) backends. ROCm is AMD's open-source GPU compute stack, providing compilers, libraries, and runtime.
**HIP Language and CUDA Compatibility**
HIP shares CUDA's syntax and semantics: kernels, shared memory, atomic operations, and synchronization primitives are nearly identical. hipify-perl and hipify-clang automate CUDA→HIP porting via string replacement and AST transformation. Successful conversion rate exceeds 95% for CUDA codebases. hipMemcpy, hipMemset, and stream operations correspond directly to CUDA equivalents, enabling straightforward library porting.
**ROCm Software Stack**
ROCm includes: HIPCC compiler (HIP→AMDGPU ISA), rocBLAS (dense linear algebra), rocFFT (FFT), rocSPARSE (sparse operations), MIOpen (deep learning kernels), HIP runtime (kernel execution, memory management), rocProfiler (performance analysis), rocDEBUG (debugger). Open-source nature enables community contributions and modifications unavailable in NVIDIA's proprietary stack.
**AMD GPU Architecture: RDNA vs CDNA**
RDNA (Radeon NAVI, compute-focused consumer GPUs) features compute units (CUs) with 64-wide wave64 execution and 256 KB LDS per CU. CDNA (MI100, MI200, MI300X—datacenter) emphasizes matrix operations: 4-wide matrix units (bf16, fp32), enhanced cache hierarchies (32 MB L2), higher memory bandwidth (HBM3). MI300X (2025) provides 192 GB HBM3 (Instinct GPU) or 256 GB HBM3e system (CPU+GPU combined die).
**Roofline Model for AMD**
AMD MI300X theoretical peak: 383 TFLOPS (fp32), 766 TFLOPS (mixed precision), 192 GB/s HBM bandwidth. Arithmetic intensity (flops/byte) determines compute-vs-memory-bound: intensive kernels (matrix ops, convolutions) utilize peak flops; bandwidth-limited kernels (reduction, sparse ops) peak at 192 GB/s theoretical max.
**Ecosystem and Adoption**
rocDNN enables deep learning portability via HIP. Major frameworks (PyTorch, TensorFlow) support ROCm via HIP. HIP adoption remains smaller than CUDA—NVIDIA's dominance and closed ecosystem create lock-in. Academic and national lab efforts drive HIP adoption (ORNL, LLNL, LANL).