salicide block
**Salicide Block (SAB)** is the **lithography-defined masking layer that selectively prevents silicide formation on designated transistor regions, resistors, or I/O structures during the self-aligned silicide (salicide) process** — enabling a single wafer to contain both low-resistance silicided logic transistors and high-sheet-resistance polysilicon or diffusion resistors needed for analog circuits, ESD protection devices, and I/O interfaces.
**Why Salicide Block Is Needed**
- The salicide process (deposit NiPt or Co → anneal → silicide forms on all exposed Si/poly) would otherwise silicide every silicon surface uniformly.
- Resistors require high sheet resistance (100–1000 Ω/□) → silicide would short them to ~1–5 Ω/□.
- ESD protection diodes need controlled resistance in their ballasting regions → silicide would reduce resistance and damage ESD robustness.
- Certain analog devices need defined series resistance → salicide must be blocked.
**Salicide Block Process Flow**
```
1. Grow/deposit thin oxide or nitride over all active areas
2. Deposit SAB layer (typically TEOS oxide or SiN, 20–50 nm)
3. Lithography: expose SAB mask (defines regions to block silicide)
4. Etch: remove SAB from logic transistors (silicide will form here)
5. Leave SAB intact on resistors / ESD / analog devices
6. Deposit NiPt metal (5–10 nm)
7. RTP anneal → NiPt silicides only on exposed Si/poly (no SAB)
8. Wet strip unreacted NiPt
9. Strip remaining SAB oxide/nitride from blocked regions
```
**Sheet Resistance Comparison**
| Region | Sheet Resistance | Application |
|--------|-----------------|-------------|
| Silicided poly | 3–8 Ω/□ | Logic gate, interconnect |
| Silicided diffusion | 5–15 Ω/□ | S/D contacts |
| SAB poly (no silicide) | 150–300 Ω/□ | Precision resistors |
| SAB diffusion (no silicide) | 80–200 Ω/□ | ESD ballast, I/O |
**Critical Design Rules for SAB**
- **SAB extension beyond active**: SAB must extend past the silicide region edge by ≥ 2× overlay tolerance to prevent silicide encroachment.
- **SAB clearance from gates**: Keep SAB edge away from gate to avoid creating a non-silicided shadow that increases source resistance.
- **Dual SAB layers**: Some processes use two different block masks for poly resistors vs. diffusion resistors (different sheet resistance targets).
**SAB in ESD Design**
- ESD protection transistors use SAB on the drain side to create a distributed resistance that spreads the ESD current and prevents thermal runaway.
- Ballasting resistance (50–200 Ω) added by SAB prevents second breakdown during high-current ESD events.
- Without SAB, silicided ESD transistors have near-zero drain resistance → current crowds → device fails at low ESD stress.
**SAB in Analog Design**
- Poly resistors with SAB: Sheet resistance ~200 Ω/□, temperature coefficient ~+1500 ppm/°C (can be tuned by doping).
- Well resistors with SAB: Sheet resistance varies widely; used for matching applications.
- Process note: SAB resistors have matching accuracy ~0.1–0.5% (σ/µ) depending on geometry and layout.
The salicide block mask is **an elegantly simple technique that enables complex mixed-signal integration on a single digital CMOS process** — by selectively inhibiting silicide with a single mask layer, foundries deliver resistor values spanning three orders of magnitude alongside minimum-geometry logic transistors, all on one wafer flow without any additional front-end process modules.