sdc constraints

**SDC (Synopsys Design Constraints)** — the industry-standard format for specifying timing requirements that guide synthesis and physical design tools. **Essential Commands** - `create_clock -period 2.0 -name clk [get_ports clk]` — Define 500MHz clock - `set_input_delay -clock clk 0.5 [get_ports data_in]` — Input arrives 0.5ns after clock - `set_output_delay -clock clk 0.3 [get_ports data_out]` — Output must be ready 0.3ns before clock - `set_false_path -from [get_clocks clkA] -to [get_clocks clkB]` — Don't time this path - `set_multicycle_path 2 -from [get_pins slow_reg/Q]` — Path has 2 cycles to resolve - `set_max_delay 5.0 -from A -to B` — Constrain specific path **Why SDC Matters** - Under-constrained: Tools don't optimize hard enough → silicon fails - Over-constrained: Tools waste area/power meeting impossible targets - Wrong constraints: Most common cause of silicon bugs in timing **CDC (Clock Domain Crossing)** - Paths between different clock domains need special handling - Synchronizer flip-flops, false path constraints, or max delay constraints **SDC** flows from synthesis through place-and-route to signoff STA — the same constraints file governs the entire back-end flow.