Self-Aligned Contact

**Self-Aligned Contact (SAC) Process** is **a semiconductor interconnect fabrication methodology where contact vias are self-aligned to device features using selective etching and deposition processes — enabling reduced parasitic capacitance, improved contact reliability, and simplified photomask requirements compared to externally-aligned contact approaches**. The self-aligned contact process exploits the fact that contact positions are naturally aligned to underlying device features (such as source or drain regions) through careful mask design and selective etch chemistry, eliminating the need for additional alignment steps that would increase manufacturing complexity and reduce manufacturing tolerance margins. The SAC process begins with the completion of device formation including gate definition, source and drain implantation, and gate spacer formation, followed by dielectric deposition (typically silicon dioxide) that covers the entire device structure including gate electrodes, source-drain regions, and interconnect lines. A photomask defines the regions where contacts are desired, and anisotropic etch chemistry selectively removes the dielectric layer to expose underlying source-drain or polysilicon regions, with the etch chemistry tuned to provide excellent selectivity to the underlying conductor layers preventing over-etch damage. The key advantage of self-aligned contacts is the elimination of overlay tolerance requirements for aligning contact vias to underlying device features, as the etch process naturally aligns contacts to the edges of gate electrodes and source-drain regions through the selectivity of the etch chemistry. This reduction in overlay tolerance enables relaxation of photomask alignment tolerances and simplification of photolithography processes, reducing manufacturing costs and improving yields by eliminating yield loss from misaligned contacts. Contact barrier deposition employs conformal film deposition (sputtering or CVD) of titanium nitride or other barrier materials to prevent copper diffusion into silicon or other semiconductor layers, typically depositing 10-30 nanometers of barrier material with precise thickness control. Contact fill employs chemical vapor deposition (CVD) or electroplating of copper to completely fill contact vias and establish low-resistance electrical connections between interconnect levels, with careful control of fill processes to achieve void-free copper without excessive void nucleation sites. **Self-aligned contact (SAC) process enables simplified contact formation through natural alignment to device features, reducing overlay tolerance requirements and manufacturing complexity.**