self-timed circuits

Self-timed asynchronous circuits replace the global clock with local handshaking protocols, making them inherently robust to process variation and voltage fluctuation. Instead of a clock edge defining when data is captured, self-timed circuits use request-acknowledge signaling between pipeline stages where a sender asserts a request when data is valid and the receiver acknowledges when data is consumed. Common protocols include four-phase return-to-zero and two-phase transition signaling with dual-rail or 1-of-N encoding providing completion detection. Self-timed circuits offer advantages in variation tolerance where speed adapts automatically to local conditions, near-zero idle power with no clock toggling, reduced EMI from avoiding synchronized switching, and average-case rather than worst-case performance. Challenges include larger area overhead from dual-rail encoding, limited commercial EDA tool support for asynchronous design, and difficulty with at-speed testing. Applications include sensor interfaces and cryptographic circuits where EMI reduction matters.