semiconductor memory technology
**Semiconductor Memory Technology** is the **device and architecture discipline responsible for storing digital data — spanning volatile memories (SRAM, DRAM) that lose data without power and non-volatile memories (NAND Flash, emerging NVM) that retain data indefinitely, with each memory type occupying a specific tier in the performance-capacity-cost hierarchy that determines system speed, power, and storage capability**.
**Memory Hierarchy**
| Level | Technology | Latency | Capacity/Die | $/GB (approx) |
|-------|-----------|---------|-------------|----------------|
| Register | SRAM (6T) | ~0.3 ns | KB | N/A |
| L1/L2 Cache | SRAM (6T/8T) | 1-5 ns | 1-32 MB | $5000+ |
| L3 Cache / eDRAM | SRAM / eDRAM | 5-20 ns | 32-256 MB | $100-500 |
| Main Memory | DRAM (DDR5/HBM) | 50-100 ns | 2-24 GB/die | $2-5 |
| Storage | 3D NAND Flash | 25-100 μs | 128-256 GB/die | $0.05-0.10 |
**DRAM Technology**
- **Cell Structure**: 1 transistor + 1 capacitor (1T1C). The capacitor stores charge representing a bit. Must be refreshed every 32-64 ms (charge leaks). Scaling challenge: maintaining sufficient capacitance as cell area shrinks.
- **DDR5**: Up to 8400 MT/s (current), 512-bit internal prefetch, on-die ECC. Dual-channel per DIMM for improved bandwidth.
- **HBM (High Bandwidth Memory)**: 3D-stacked DRAM (4-16 dies via TSV) with 1024-bit bus width. HBM3e: 9.8 Gbps/pin, 1.2 TB/s per stack. The bandwidth-critical memory for AI accelerators.
- **Scaling**: DRAM pitch scaling has slowed dramatically. New architectures under development: buried word line, 4F² cell, EUV for DRAM, and potential transition to capacitor-less DRAM (gain cell).
**3D NAND Flash**
- **Cell Structure**: Floating-gate or charge-trap transistors stacked vertically (128-300+ layers). SLC (1 bit/cell), MLC (2), TLC (3), QLC (4), PLC (5) — each level increases density but reduces endurance and speed.
- **Vertical Scaling**: Add more layers per die. Samsung/SK Hynix/Micron now at 200-300 layers. Stack height limited by mechanical stress, etch aspect ratio (>100:1), and yield.
- **Controller Intelligence**: ECC (LDPC), read-retry algorithms, wear leveling, and garbage collection are implemented in the flash controller to manage the inherent unreliability of NAND cells.
**Emerging Non-Volatile Memory**
- **STT-MRAM**: Spin-Transfer Torque Magnetic RAM. Non-volatile, DRAM-like speed, unlimited endurance. used as embedded non-volatile memory in SoCs (replacing eFlash at advanced nodes where eFlash is difficult to scale).
- **PCM (Phase-Change Memory)**: Exploits chalcogenide material phase transitions between amorphous (high resistance) and crystalline (low resistance). Intel Optane used PCM for storage-class memory (deprecated 2022, but technology continues elsewhere).
- **RRAM/ReRAM**: Resistive switching in metal oxide thin films. Simple 2-terminal structure enabling high-density crossbar arrays. Promising for in-memory computing (analog matrix-vector multiplication).
Semiconductor Memory Technology is **the storage infrastructure that determines how much data a system can access and how quickly** — a hierarchy of technologies from registers to flash, each optimized for a different point in the speed-capacity-cost trade-off space that defines computing system performance.