semiconductor yield
**Semiconductor Yield** is the **percentage of functional dies on a processed wafer, determined by the interaction of defect density, die area, and defect distribution** — the single most important metric for fab profitability, where a 1% yield improvement on a high-volume product can represent tens of millions of dollars in annual revenue.
**Yield Formula (Poisson Model)**
$Y = e^{-D_0 \times A}$
where:
- Y = die yield (fraction of good dies).
- D₀ = defect density (defects per cm²).
- A = die area (cm²).
**Negative Binomial Model (More Realistic)**
$Y = (1 + \frac{D_0 \times A}{\alpha})^{-\alpha}$
- α = cluster parameter (how clustered defects are).
- α → ∞: Poisson (random defects).
- α = 1-5: Typical fab (defects are clustered).
- Clustering means some dies get many defects (killed) while others get none (good) → higher yield than Poisson predicts.
**Yield Components**
| Component | Description | Typical Value |
|-----------|------------|---------------|
| Wafer yield | Good wafers / total wafers started | 95-99% |
| Limited yield | Dies fully within wafer edge | 85-95% (depends on die size) |
| Gross yield | Dies passing basic functional test | 90-98% |
| Parametric yield | Dies meeting ALL specifications | 80-95% |
| Overall yield | Product of all components | 70-90% |
**Yield by Die Area**
Assuming D₀ = 0.1 defects/cm² (mature process):
| Die Area | Poisson Yield | Example Chip |
|----------|--------------|-------------|
| 50 mm² | 95.1% | Mobile SoC |
| 100 mm² | 90.5% | Desktop CPU |
| 200 mm² | 81.9% | Server CPU |
| 400 mm² | 67.0% | GPU (large) |
| 800 mm² | 44.9% | Reticle-limit GPU |
- Large dies have dramatically worse yield — drives chiplet/disaggregation trend.
**Yield Learning Curve**
- New process technology: Yield starts at 20-40% → improves over 12-24 months → matures at 85-95%.
- **Learning rate**: Defect density halves every 6-12 months during ramp.
- d₀ mature (advanced node): 0.05-0.15 defects/cm².
**Yield Enhancement Strategies**
- **Redundancy**: Spare rows/columns in memory arrays (SRAM repair).
- **Smaller dies**: Chiplet architecture — four 200mm² chiplets vs. one 800mm² monolithic.
- **Defect-tolerant design**: Critical paths duplicated, error-correction on buses.
- **Process improvements**: Reduce particle counts, improve CD uniformity, better CMP.
**Economic Impact**
- 300mm wafer cost at 3nm: ~$20,000-30,000.
- 100mm² die: ~500 dies per wafer.
- At 80% yield: 400 good dies → $50-75 per die manufacturing cost.
- At 60% yield: 300 good dies → $67-100 per die → 33% more expensive.
Semiconductor yield is **the ultimate measure of manufacturing excellence** — it directly determines the cost per transistor delivered to customers, and the relentless focus on yield improvement is what has enabled the semiconductor industry to deliver exponentially more computation at declining cost per unit for decades.