SerDes

```svg ```SerDes (Serializer/Deserializer)** is the circuit that converts a wide bundle of parallel bits into a single high-speed serial stream for transmission, and back again at the far end. The **PHY** (physical layer) is the broader analog/mixed-signal block that contains the SerDes plus everything needed to actually push bits onto a wire and recover them: line drivers, equalizers, clock recovery, and encoding. Nearly every fast link in modern computing — PCIe, Ethernet, USB, HBM interfaces, and die-to-die chiplet links — is built on SerDes/PHY blocks. They are where the digital world meets the messy physics of real channels, and increasingly where the hardest chip-design problems live.\n\n```svg\n\n```\n\n**The core idea is trading width for speed.** Routing 64 parallel wires across a board at a modest clock is expensive in pins, area, and skew — the wires drift out of alignment. A SerDes instead sends the data over one differential pair at a very high rate, so a link needs only a couple of wires per lane. Fewer pins and connectors, at the cost of running the serial line at multi-gigahertz to tens-of-gigahertz symbol rates. This is the trade every high-speed interconnect makes.\n\n**Real channels destroy the signal, so the PHY spends most of its effort undoing that.** A PCB trace or cable attenuates high frequencies and smears each symbol into its neighbors (inter-symbol interference). By the time the signal reaches the receiver, its "eye" — the open region in an overlaid plot of many bit transitions — can be almost completely closed. The PHY fights back with equalization: transmit pre-emphasis/FFE that boosts high frequencies before sending, and receive CTLE and DFE that flatten and cancel the channel's distortion. Good equalization is what re-opens the eye.\n\n**The eye diagram is the universal measure of link health.** Overlaying many received bit periods produces an "eye"; a wide-open eye means the receiver can cleanly distinguish 1s from 0s with timing and voltage margin, while a closed eye means errors. Nearly all SerDes bring-up, characterization, and debugging revolves around opening and measuring the eye, and every equalization knob is tuned to widen it.\n\n**The receiver must recover the clock, because none is sent.** High-speed serial links do not ship a separate clock wire; instead a clock-data recovery (CDR) circuit extracts timing directly from the data transitions and locks onto it. This is why line coding (like 8b/10b or 128b/130b scrambling) matters — it guarantees enough transitions for the CDR to stay locked and keeps the signal DC-balanced.\n\n**Pushing past ~50 Gbps per lane forced a move to PAM4.** Simple on/off (NRZ) signaling sends one bit per symbol; to keep doubling rates without doubling frequency, modern SerDes use PAM4, which encodes two bits per symbol using four voltage levels. That squeezes more data through the same channel bandwidth but shrinks the vertical eye and demands far more sophisticated equalization and error correction — which is why 112G and 224G SerDes are among the most challenging analog blocks on a leading-edge chip.\n\n| Element | Job | Lives in |\n|---|---|---|\n| Serializer / Deserializer | parallel ↔ serial conversion | TX / RX |\n| Driver + FFE/pre-emphasis | shape signal before the channel | TX PHY |\n| CTLE / DFE equalizers | undo channel loss & ISI | RX PHY |\n| CDR | recover the clock from data | RX PHY |\n| Encoding (NRZ / PAM4) | bits-per-symbol & DC balance | both |\n\nRead SerDes/PHY through a *fight-the-channel* lens rather than a *wire* lens: the serializer is the easy part; the real engineering is recovering a clean stream after a lossy trace has done its worst. Almost the entire PHY — pre-emphasis, CTLE, DFE, CDR, FEC — exists to re-open an eye that physics keeps trying to close, and it is exactly this analog battle that sets the practical ceiling on how fast PCIe, Ethernet, and chiplet links can run.\n