shallow trench isolation sti

**Shallow Trench Isolation (STI)** is **the dominant isolation technology for sub-250nm CMOS processes that electrically isolates adjacent transistors by etching trenches into silicon and filling them with dielectric material — providing superior isolation density, reduced junction capacitance, and better latch-up immunity compared to LOCOS isolation, while introducing mechanical stress effects that impact device performance**. **STI Process Flow:** - **Pad Oxide and Nitride**: grow thin pad oxide (5-10nm) to relieve stress, deposit 100-200nm silicon nitride hard mask by LPCVD at 700-800°C; nitride serves as polish stop during CMP and protects active areas during trench etch - **Trench Etch**: pattern and etch trenches 200-400nm deep using Cl₂/HBr/O₂ plasma chemistry; etch profile must be controlled to 85-90° sidewall angle; rounded trench corners (corner rounding by H₂ anneal or wet etch) prevent stress concentration and gate oxide thinning - **Liner Oxidation**: thermal oxidation at 900-1000°C grows 5-15nm liner oxide on trench sidewalls and bottom; liner oxide passivates etch damage, reduces interface states (Dit < 10¹¹ cm⁻²eV⁻¹), and provides high-quality dielectric interface - **Trench Fill**: high-density plasma (HDP) CVD oxide or sub-atmospheric CVD (SACVD) TEOS fills trenches at 400-600°C; HDP combines deposition and sputtering for void-free fill of high-aspect-ratio trenches (3:1 to 6:1); ozone-TEOS provides excellent gap-fill with lower ion damage **CMP and Nitride Strip:** - **Oxide CMP**: removes excess oxide and planarizes surface using ceria-based slurry; oxide removal rate 200-400nm/min with oxide:nitride selectivity >20:1; CMP stops on nitride hard mask - **Dishing and Erosion**: wide trenches experience dishing (center polishes faster); dense trench arrays experience erosion (pattern-dependent removal); dummy fill and CMP-aware layout rules minimize topography variation to <20nm - **Nitride Strip**: hot phosphoric acid (H₃PO₄ at 150-180°C) removes nitride hard mask with high selectivity to oxide (>50:1) and pad oxide; strip rate 5-10nm/min requires 20-40 minute process - **Pad Oxide Removal**: dilute HF (DHF 100:1 or 50:1) removes pad oxide; this step defines the final active area height relative to STI surface; active area recess of 0-10nm is typical **Stress Effects:** - **Compressive Stress**: oxide-filled trenches exert compressive stress on adjacent active areas; stress magnitude 200-800MPa depends on trench depth, width, and oxide density; affects both NMOS and PMOS mobility - **Layout Dependence**: stress varies with active area width and spacing; narrow active areas (<200nm) experience higher stress than wide areas; stress-aware design and modeling required for accurate performance prediction - **Stress Mitigation**: liner oxidation conditions, HDP vs SACVD fill, and post-fill anneals modify stress magnitude; some processes intentionally tune STI stress to complement or enhance strain engineering effects - **Inverse Narrow Width Effect (INWE)**: threshold voltage increases in narrow transistors due to STI stress and corner effects; Vt shift of 50-150mV for width <200nm requires width-dependent Vt adjustment in design **Isolation Performance:** - **Leakage Current**: STI provides >10¹² Ω isolation resistance between adjacent devices; junction-to-junction leakage <1fA/μm at 1V bias; superior to LOCOS which suffers from bird's beak encroachment and higher capacitance - **Junction Capacitance**: STI reduces junction capacitance 30-50% vs LOCOS by eliminating bird's beak and providing abrupt active-to-isolation transition; critical for high-speed circuits where parasitic capacitance limits performance - **Latch-up Immunity**: deep trenches (300-400nm) provide effective barrier to parasitic bipolar action; STI-isolated CMOS has 2-3× higher latch-up trigger current than LOCOS - **Scalability**: STI scales effectively to sub-50nm active area widths; minimum trench width 50-100nm limited by lithography and gap-fill capability; enables aggressive area scaling for SRAM and logic **Advanced STI Variants:** - **Stress-Relieved STI**: additional liner or multi-layer fill structures reduce stress on active areas; improves mobility in stress-sensitive devices but adds process complexity - **Air-Gap STI**: partially remove oxide from wide trenches and seal with dielectric cap, creating air gaps (k=1) for reduced parasitic capacitance; used in RF and high-speed applications - **Recessed STI**: over-polish oxide to recess STI surface 10-30nm below active area; reduces gate-to-STI fringe capacitance and improves short-channel control in FinFET and planar SOI devices Shallow trench isolation is **the foundational isolation technology that enabled CMOS scaling from 250nm to 7nm nodes — its superior density, electrical performance, and scalability make it indispensable for modern integrated circuits, despite the added complexity of stress management and CMP-related challenges**.