shallow trench isolation sti

**Shallow Trench Isolation (STI)** is the **standard CMOS isolation technique that electrically separates adjacent transistors by etching shallow trenches (~200-350nm deep) into the silicon substrate and filling them with deposited silicon dioxide — replacing the older LOCOS (Local Oxidation of Silicon) process with a fully planar isolation structure that scales to the smallest technology nodes without the bird's beak encroachment that limited LOCOS density**. **Why STI Replaced LOCOS** LOCOS grew thick oxide in isolation regions by thermal oxidation through a silicon nitride mask. The oxidation undercut the mask edges (bird's beak), consuming valuable active area and creating a non-planar surface. At minimum isolation widths below ~0.4 μm, the bird's beaks from adjacent regions nearly merged, making LOCOS unscalable. STI provides vertical isolation walls with no lateral encroachment and a planar surface after CMP. **STI Process Flow** 1. **Pad Oxide and Nitride**: Grow thin thermal oxide (~5-10nm) on silicon. Deposit silicon nitride (~80-150nm) by LPCVD. The nitride serves as a CMP stop layer and etch mask. 2. **Trench Patterning**: Lithography and dry etch define the trench pattern. The etch cuts through the nitride, pad oxide, and into the silicon substrate to a depth of 200-350nm. Trench profile control is critical — slightly tapered sidewalls (85-88°) provide better fill than perfectly vertical walls. 3. **Liner Oxidation**: A thin thermal oxide (~3-10nm) is grown on the trench sidewalls and bottom. This liner rounds the trench corners (reducing electric field concentration), repairs etch damage to the silicon surface, and provides a high-quality Si/SiO₂ interface. 4. **Trench Fill**: The trench is filled with silicon dioxide using HDP-CVD (high-density plasma CVD) or FCVD (flowable CVD). HDP-CVD provides simultaneous deposition and sputter-back for void-free fill of narrow trenches. FCVD is used at advanced nodes where aspect ratios exceed HDP-CVD capability — the flowable oxide fills narrow trenches like a liquid before being converted to solid SiO₂ by curing. 5. **CMP Planarization**: Chemical-mechanical polishing removes the oxide overburden, stopping on the silicon nitride layer. The resulting surface is planar — oxide in the trenches is flush with the nitride on the active areas. 6. **Nitride Strip**: Hot phosphoric acid (H₃PO₄ at 160°C) selectively removes the nitride CMP stop layer, leaving a slightly recessed STI oxide relative to the silicon active area surface. **Scaling Challenges** - **Narrow Trench Fill**: At sub-14nm nodes, STI trench widths shrink below 20nm. High-aspect-ratio narrow trenches require FCVD or multi-step fill/etch-back processes to avoid seam voids. - **STI Stress Effects**: The isolation oxide exerts compressive stress on the adjacent silicon channel, affecting carrier mobility. For FinFET and GAA nodes, STI must be carefully integrated with the fin or nanosheet formation to control stress profiles. - **Recess Control**: The amount of STI oxide recessed below the fin top determines the fin height exposed to the gate. This recess is a critical dimension (±1nm tolerance) at FinFET/GAA nodes. Shallow Trench Isolation is **the foundation separating every transistor from its neighbors** — a trench of oxide carved and filled in the silicon surface that has served as the isolation standard for over 25 years, scaling from 250nm minimum width to 10nm and adapting from planar transistors through FinFETs to nanosheets.