STI CMP process
**Shallow Trench Isolation (STI) CMP** is the **chemical mechanical planarization step that removes excess oxide deposited over filled isolation trenches to create a planar surface flush with the silicon active area**, where precise stopping on the SiN hard mask and minimizing dishing/erosion are critical — as STI CMP uniformity directly impacts gate oxide thickness consistency and transistor threshold voltage matching across the entire chip.
**STI Process Context**: After trench etching and liner oxidation, the trenches are filled with HDP or HARP oxide (significantly overfilling to ensure complete gap-fill). The resulting wafer surface has large topography — oxide over the trenches is 200-400nm higher than the active silicon regions protected by the SiN/pad oxide stack. CMP removes this excess oxide, stopping on the SiN hard mask with high selectivity.
**CMP Requirements for STI**:
| Parameter | Specification | Consequence of Miss |
|-----------|-------------|--------------------|
| Oxide removal rate | 200-400 nm/min | Throughput impact |
| Oxide:SiN selectivity | >30:1 (ceria slurry) | SiN erosion if low |
| Within-wafer uniformity | <3% WIWNU | V_th variation |
| Dishing | <5nm for 10μm trench | Step height at gate |
| Erosion | <3nm for dense active | Active area thinning |
| SiN residual thickness | Controlled ±2nm | Downstream integration |
**Ceria-Based Slurry**: The key enabling technology for STI CMP. Cerium oxide (CeO₂) nanoparticles have a unique chemical interaction with SiO₂: the Ce³⁺/Ce⁴⁺ redox couple catalyzes SiO₂ removal through a "chemical tooth" mechanism, providing very high oxide removal rates. Critically, ceria has inherently high selectivity to SiN (which lacks the silanol surface chemistry), enabling reliable stopping on the SiN hard mask without excessive overpolish.
**Dishing and Erosion Control**: **Dishing** occurs in wide trench regions where the polishing pad deforms into the trench, removing oxide below the desired target level. **Erosion** occurs in dense active regions where thin oxide between closely-spaced active areas is over-polished. Mitigation: **reverse etch-back** (partial oxide etch before CMP to reduce topography); **multi-step CMP** (fast bulk removal followed by gentle final polish with higher selectivity); and **design rules** requiring minimum/maximum STI width and active density targets.
**Pattern Density Effects**: CMP removal rate depends on local pattern density — regions with high oxide density (wide trenches, few active areas) polish slower than regions with low oxide density (many active areas, narrow trenches). This causes systematic across-chip thickness variation correlated with layout pattern. Design-level solutions include: STI fill patterns in large open areas and active area density rules.
**Post-CMP Processing**: After STI CMP, the SiN hard mask is stripped (hot H₃PO₄), and the pad oxide is removed (dilute HF). The resulting surface should have the silicon active areas co-planar with the STI oxide fill, ready for gate oxidation. Any residual step height between active and STI translates directly into gate oxide thickness variation at the isolation edge, impacting transistor characteristics.
**STI CMP exemplifies the critical role of planarization in modern CMOS — where a polishing step performed millimeters away from the eventual transistor channel determines the gate oxide uniformity that controls threshold voltage matching, making CMP precision as important as lithographic precision for device performance.**