silicide bridging

**Silicide Bridging** is a **defect where silicide forms unintentionally across isolation regions** — creating a conductive path (short circuit) between adjacent transistor terminals (e.g., gate-to-source, drain-to-drain of neighboring devices). **What Causes Silicide Bridging?** - **Root Causes**: - **Spacer Failure**: Thin or defective spacers expose Si sidewall -> silicide connects gate to S/D. - **STI Divot**: Etching or CMP creates a recessed trench at the STI edge, exposing Si beneath the isolation. - **Metal Migration**: During salicide anneal, metal migrates over the spacer or STI, forming silicide where it shouldn't. - **Detection**: Abnormal leakage current between adjacent nodes. **Why It Matters** - **Yield Killer**: A single silicide bridge can short-circuit a transistor, killing the die. - **Process Control**: Spacer integrity and STI corner profile are critical to prevent bridging. - **Scaling**: As device pitch shrinks, the distance between terminals decreases, making bridging more likely. **Silicide Bridging** is **an unwanted conductive shortcut** — where the silicide formation process accidentally creates connections between terminals that should be isolated.