silicon carbide sic wafer
**Silicon Carbide (SiC) Wafer Technology** is the **wide-bandgap semiconductor substrate essential for high-voltage, high-temperature, and high-efficiency power electronics — where SiC's superior material properties (3× bandgap, 10× breakdown field, 3× thermal conductivity vs. silicon) enable power devices that reduce switching losses by 50-80% in electric vehicle inverters, solar inverters, and industrial motor drives, with wafer quality and cost being the primary barriers to broader adoption**.
**SiC Material Properties**
| Property | Silicon | 4H-SiC | Advantage |
|----------|---------|--------|-----------|
| Bandgap (eV) | 1.12 | 3.26 | Higher operating temperature |
| Breakdown field (MV/cm) | 0.3 | 2.8 | Thinner drift layers for same voltage |
| Thermal conductivity (W/m·K) | 150 | 370 | Better heat dissipation |
| Electron saturation velocity (cm/s) | 1×10⁷ | 2×10⁷ | Higher switching frequency |
| Intrinsic carrier concentration | 10¹⁰/cm³ | 10⁻⁹/cm³ | Lower leakage at high temp |
**SiC Crystal Growth**
SiC boules are grown using Physical Vapor Transport (PVT, modified Lely method):
- SiC powder source heated to 2200-2500°C in an induction-heated graphite crucible under argon/nitrogen atmosphere.
- SiC sublimes and deposits on a cooler SiC seed crystal at the top of the crucible.
- Growth rate: 0.1-0.5 mm/hour (extremely slow vs. Si Czochralski at 1-2 mm/min).
- Typical boule: 150 mm diameter × 30-50 mm length → yields ~20-40 wafers after slicing, grinding, and polishing.
- **200 mm transition**: Wolfspeed, Coherent (II-VI), and STMicroelectronics are transitioning from 150 mm to 200 mm wafers (2024-2026) to reduce per-device cost by 2-3×.
**Defect Challenges**
SiC crystal growth is plagued by defects due to the extreme growth conditions:
- **Micropipe Defects**: Hollow-core screw dislocations (1+ μm diameter). Killer defect — any device intersecting a micropipe fails. Modern SiC wafers: <0.1 micropipes/cm² (was >100/cm² in the 1990s).
- **Basal Plane Dislocations (BPD)**: BPDs convert to stacking faults under forward-bias operation, causing increased on-resistance (Vf drift). BPD density: 100-500/cm² in state-of-the-art wafers. BPD-to-TED conversion during epitaxy reduces this to <1/cm² at the active device layer.
- **Threading Screw Dislocations (TSD)**: 100-300/cm². Impact on gate oxide reliability under investigation.
- **Threading Edge Dislocations (TED)**: 1000-5000/cm². Generally benign for device performance.
**SiC Epitaxy**
Device-quality SiC is grown epitaxially on the SiC substrate using Chemical Vapor Deposition (CVD):
- Precursors: SiH₄ (silane) + C₃H₈ (propane) or trichlorosilane + ethylene in H₂ carrier gas.
- Temperature: 1500-1650°C.
- Growth rate: 5-50 μm/hour (higher for thick drift layers in high-voltage devices).
- Doping: N-type (nitrogen), P-type (aluminum) — in-situ during growth.
- Thickness: 5-30 μm for 650-1200 V devices; 100+ μm for 3.3-15 kV devices.
**Cost and Volume**
SiC wafer cost: $500-$1500 per 150 mm wafer (vs. $10-$50 for silicon). The wafer represents 30-50% of the final power module cost. Driving cost reduction: larger diameter (200 mm), faster growth, longer boules, higher yield.
SiC Wafer Technology is **the material foundation that enables the electrification revolution** — the wide-bandgap semiconductor substrate whose superior physical properties translate directly into the efficiency, power density, and temperature capability gains that make electric vehicle drivetrains, renewable energy converters, and industrial power systems commercially competitive.