epitaxial growth semiconductor
**Epitaxial Growth** is the **semiconductor crystal growth process that deposits single-crystalline material on a crystalline substrate where the deposited film adopts the substrate's crystal orientation — used in CMOS for channel materials, strain-engineering source/drain regions, SiGe/Si superlattice formation for GAA nanosheets, and III-V integration, where film quality (defect density <10² cm⁻², thickness uniformity ±1%, composition control ±0.5%) directly determines transistor performance and yield**.
**Why Epitaxy Is Essential**
Bulk silicon wafers provide the starting crystal, but many CMOS applications require silicon layers with different doping levels, compositions (SiGe, Si:C, Si:P), or crystal quality than the bulk substrate. Epitaxial growth builds these engineered layers atom-by-atom on the existing crystal, maintaining single-crystal quality while adding designed-in properties.
**Growth Methods**
- **RPCVD (Reduced Pressure Chemical Vapor Deposition)**: The standard tool for silicon and SiGe epitaxy. Gas precursors (SiH₄ or SiH₂Cl₂ for Si, GeH₄ for Ge, B₂H₆ for boron doping, PH₃ for phosphorus) are flowed over the heated wafer (550-900°C) at reduced pressure (10-100 Torr). Surface reactions build the crystal one layer at a time. Single-wafer processing for advanced nodes (Applied Materials Centura Epi, ASM Epsilon).
- **MBE (Molecular Beam Epitaxy)**: Ultra-high vacuum (~10⁻¹⁰ Torr). Elemental sources are evaporated and directed at the heated substrate. Atomic-level control but very low throughput. Used for research and III-V compound semiconductors, not for CMOS production.
- **ALD-Like Epitaxy**: At temperatures <400°C, cyclic deposition-etch processes can grow epitaxial layers with ALD-level thickness control. Under development for back-end-compatible epitaxy.
**Selective Epitaxial Growth (SEG)**
The key capability for CMOS: epitaxial growth occurs only on exposed silicon surfaces (nucleation on crystal), not on adjacent dielectric surfaces (SiO₂, SiN). This selectivity enables source/drain epitaxy in the transistor recess without depositing material on the isolation oxide or gate spacers. Selectivity is achieved by adding an etchant gas (HCl) that removes any non-crystalline nuclei on dielectric surfaces while the crystalline growth on silicon proceeds faster than the etch.
**Critical Epitaxy Steps in Advanced CMOS**
1. **Si/SiGe Superlattice (GAA)**: 3-4 pairs of alternating Si (5-7nm) and SiGe (8-12nm) layers with atomically sharp interfaces. Ge fraction must be uniform ±0.5% within each layer. Total stack height 60-80nm with ±1% thickness control per layer.
2. **S/D Stressor Epitaxy**: Diamond-shaped SiGe (40-60% Ge) fills for PMOS, Si:P fills for NMOS. In-situ doping >5×10²⁰ cm⁻³. Must merge between adjacent fins without void formation.
3. **Channel Epitaxy**: SiGe channel layers for PMOS mobility enhancement. Thin (3-5nm) with precise Ge content for threshold voltage tuning.
Epitaxial Growth is **the crystal-building art that gives every advanced transistor its engineered channel, its strained source/drain, and its nanosheet stack** — growing semiconductor material one atomic plane at a time with the precision that determines whether a process node delivers its promised performance.