epitaxial growth semiconductor
**Epitaxial Growth in Semiconductor Manufacturing** is the **crystal growth technique that deposits single-crystalline thin films on a crystalline substrate — used to grow strained SiGe and Si:P source/drain regions, nanosheet superlattice stacks, channel materials, and buried layers with atomic-level composition control, where the epitaxial film's strain, doping, thickness, and interface quality directly determine transistor performance metrics including drive current, leakage, and threshold voltage**.
**Epitaxy Fundamentals**
The substrate crystal acts as a template — deposited atoms arrange themselves in the same crystal orientation. Epitaxial films differ from the substrate only in composition or doping. The process occurs in a chemical vapor deposition (CVD) chamber at 400-900°C using gas-phase precursors.
**Key Precursors**
| Material | Precursor Gases | Temperature | Application |
|----------|----------------|-------------|-------------|
| Si | SiH₄ (silane), SiH₂Cl₂ (DCS) | 600-900°C | Channels, wells |
| SiGe | SiH₄ + GeH₄ | 400-700°C | PMOS S/D (strain) |
| Si:P | SiH₄ + PH₃ | 550-700°C | NMOS S/D |
| Si:B | SiH₄ + B₂H₆ | 550-700°C | PMOS contacts |
| SiGe:B | SiH₄ + GeH₄ + B₂H₆ | 400-650°C | PMOS S/D (high strain) |
**Selective Epitaxial Growth (SEG)**
Growth occurs only on exposed silicon surfaces, not on dielectric (oxide, nitride). Selectivity is achieved through HCl addition to the gas mixture — HCl etches nuclei on dielectric surfaces faster than they grow, while crystalline growth on silicon proceeds. SEG is used for:
- **S/D Raised Epitaxy**: Grow SiGe or Si:P selectively on the source/drain regions of FinFET/GAA transistors. The epitaxial region is in-situ doped to >10²¹ cm⁻³.
- **Embedded SiGe (eSiGe)**: SiGe in PMOS S/D trenches creates compressive strain in the channel, boosting hole mobility by 30-50%. Ge content: 25-50% depending on node.
**Strain Engineering**
- **Compressive Strain (PMOS)**: SiGe (larger lattice constant than Si) in the S/D compresses the channel, improving hole mobility. Higher Ge content = more strain = higher mobility, but too much causes dislocations.
- **Tensile Strain (NMOS)**: Si:P with high phosphorus content creates slight tensile strain. Additionally, SiGe sacrificial layers in the GAA nanosheet stack create tensile strain in the released Si channels after removal.
**Nanosheet Superlattice Epitaxy**
For GAA transistors, the alternating Si/SiGe superlattice stack must meet extreme specifications:
- **Thickness Precision**: ±0.3 nm across the wafer for each layer (5-8 nm thick). Thickness variation shifts device threshold voltage.
- **Composition Control**: SiGe Ge% uniformity within ±0.5% across the wafer — affects etch selectivity during channel release.
- **Interface Abruptness**: Si/SiGe transitions must be atomically abrupt (<1 nm) to ensure clean channel release.
- **Defect Density**: Zero misfit dislocations in the strained stack — any relaxation creates threading dislocations that kill transistors.
Epitaxial Growth is **the crystal engineering foundation of modern transistors** — the deposition technique that creates the precisely-strained, doped, and dimensioned semiconductor films from which every charge-carrying channel, every current-injecting source/drain, and every performance-enhancing strain structure is built.