Silicon Grown Junction 1954 Clean and Passivate

# Clean and Passivate: Chemical Oxidation, Surface State Quenching, and Silicone Potting

Passing the functional electrical test in Step 32 confirms that the contacted silicon matchstick exhibits genuine current gain and high breakdown voltage—but exposed silicon surfaces remain acutely vulnerable to ambient chemical poisoning and surface state degradation. In 1954, thermal $\text{SiO}_2$ oxide passivation was still years in the future (pioneered by Martin Atalla at Bell Labs in 1957). The bare silicon crystal emerged from pulse bonding with uncoordinated surface atoms and dangling bonds creating a high density of fast surface states ($N_{ss} > 10^{12}\ \text{cm}^{-2}\cdot\text{eV}^{-1}$). These states act as lethal carrier recombination centers that bleed away injected emitter electrons, elevate surface recombination velocity ($s > 10^4\ \text{cm/s}$), and cause collector leakage current ($I_{\text{CBO}}$) to drift uncontrollably under high-temperature operating fields. Before the device could be permanently hermetically encapsulated in Step 34, Texas Instruments implemented an essential two-part surface stabilization sequence: controlled chemical oxidation to quench dangling bonds beneath a stoichiometric native oxide film, followed by application of high-temperature electronic-grade silicone grease to isolate the junctions from trace humidity.

## 1. Dangling Bonds, Surface Recombination Velocity, and Pre-1957 Passivation

$$s = \frac{v_{th} \, \sigma \, N_{ss}}{2} \quad \text{and} \quad \alpha = \gamma \cdot \left(1 - \frac{W_B^2}{2 L_n^2} - \frac{s \cdot A_{\text{surface}} \cdot W_B}{D_n \cdot A_{\text{bulk}}}\right)$$

Surface phenomena dominate the physics of narrow grown-junction devices prior to can enclosure:
1. The Threat of Uncoordinated Dangling Bonds:
Where the periodic crystal lattice terminates at the outer surface of the $25\ \mu\text{m}$ base stripe, silicon valence electrons remain unpaired. These dangling bonds generate localized energy levels near the center of the forbidden energy gap ($E_g = 1.12\ \text{eV}$). According to Shockley-Read-Hall theory, mid-gap traps maximize electron-hole recombination rates:
* Minority electrons injected from the emitter diffuse through the base toward the collector.
* If they encounter the perimeter surface, high surface state density ($N_{ss} > 10^{12}\ \text{cm}^{-2}\cdot\text{eV}^{-1}$) pulls them into rapid non-radiative recombination sinks.
* This surface leakage path severely degrades the base transport factor, reducing common-base gain $\alpha$ by $5\text{ to }10\%$.
2. Controlled Chemical Oxidation:
To quench these active electronic states, Texas Instruments immersed the assembled header in a controlled oxidizing bath (dilute electronic-grade hydrogen peroxide $\text{H}_2\text{O}_2$ or hot deionized water cascade):
* Oxygen atoms chemisorb onto the outer lattice, bonding with uncoordinated silicon atoms to form a dense, hydrated native silicon dioxide layer ($\text{SiO}_x$, $15\text{ to }20\ \text{\AA}$ thick).
* This passivation skin terminates the dangling bonds, reducing fast surface trap density $N_{ss}$ by an order of magnitude and driving surface recombination velocity $s$ from $> 10^4\ \text{cm/s}$ down to $< 500\ \text{cm/s}$.

## 2. Real Diagram: Chemical Surface Passivation and Silicone Potting Barrier

Step 33: Chemical Surface Passivation and Silicone Grease Potting quenching dangling surface states and potting with high-temperature silicone prior to can sealing Surface State Quenching (15 Å Oxide) Unpassivated Surface: High Recombination Si Si Si Dangling Bonds s > 10⁴ cm/s (Loss) Passivated Surface: Chemical Native Oxide Si O Si O Si O Tied Bonds s < 500 cm/s (Stable) ✓ Gain preserved prior to encapsulation Silicone Grease Potting & Clearance Kovar Header Base Base Base Pin Dow Corning Silicone Potting d > 0.5 mm • Hydrophobic methyl-siloxane barrier • Thermal stability up to 200°C (military grade) • Dielectric strength > 15 kV/mm stops arc-over chemical passivation and silicone potting stabilize surface states and lock in high-temperature reliability

## 3. High-Temperature Silicone Potting and Inter-Lead Dielectric Clearance

$$V_{\text{breakdown}} \approx E_{\text{diel}} \cdot d_{\text{separation}} \quad \text{where } E_{\text{silicone}} > 15\ \text{kV/mm}$$

Silicon transistors were engineered specifically for extreme thermal environments ($150^\circ\text{C}$), imposing unique passivation requirements:
1. The Failure of Conventional Organic Potting:
In 1951 germanium transistors, assemblies were often coated with waxes, petroleum jellies, or low-temperature casting resins. However, when heated above $100^\circ\text{C}$, these organic compounds melt, release corrosive volatile fractions, or carbonize into conductive paths.
2. Electronic-Grade Silicone Potting:
Texas Instruments selected Dow Corning high-viscosity silicone grease:
* Inorganic $\text{Si}\text{--}\text{O}\text{--}\text{Si}$ Backbone: Possesses exceptional bond energy ($452\ \text{kJ/mol}$), ensuring thermal stability without decomposition up to $+200^\circ\text{C}$.
* Hydrophobic Methyl Termination ($-\text{CH}_3$): Completely repels water molecules, preventing condensation of desorbed moisture across the microscopic $25\ \mu\text{m}$ base stripe during thermal cycling.
* Elastic Shock Absorption: Cushions the fragile gold-gallium gooseneck base wire against mechanical shock ($> 500\ g$) and vibration.
3. Inter-Lead Clearance Verification:
Before encapsulation, optical inspection verifies that the spatial gap between the base lead wire and adjacent header posts satisfies $d_{\text{separation}} \ge 0.5\ \text{mm}$:
* Because the collector operates at voltages up to $50\ \text{V}$, inadequate air clearance risks particulate bridging or electrostatic arc discharge.
* Encapsulating the wire junction in silicone grease increases the dielectric withstand field from $E_{\text{air}} \approx 3\ \text{kV/mm}$ to $E_{\text{silicone}} > 15\ \text{kV/mm}$, providing a $10\times$ electrical safety buffer.

Collector Leakage Stability Under 150 °C Thermal Bias Stress silicone-potted junction preserves nanoampere stability; unpassivated surface drifts exponentially stress duration at 150 °C (hours) → collector reverse leakage I_CBO (nA, log scale) 100 nA Reliability Limit Unpassivated: Leakage Runaway Silicone Potted: Stable < 20 nA t = 0 (15 nA) silicone grease potting shields the crystal from humidity and permanently arrests surface leakage drift

## Clean and Passivate's Place in the Process Lineage

Cleaning and passivating is step thirty-three of this project's 1954 silicon grown-junction transistor series — following the intermediate verification of transistor action, and preceding hermetic can enclosure. It represents the vital chemical protection bridge between bare semiconductor physics and robust physical packaging, quenching active surface recombination states and sealing the delicate $25\ \mu\text{m}$ junction zone beneath high-temperature silicone grease. Step thirty-four, hermetically seal can, subjects the assembly to vacuum bakeout and resistance-welds the metal enclosure under dry inert nitrogen.

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