Silicon Grown Junction 1954 Hermetically Seal Can

# Hermetically Seal Can: 200°C Vacuum Bakeout, Dry Nitrogen Backfill, and Projection Welding

While early 1951 germanium transistors were frequently packaged in molded plastic or lacquer coatings that leaked moisture over years of service, Texas Instruments designed the 1954 silicon transistor for the most hostile environments known to military avionics and guided missiles. A silicon bar capable of operating at $150^\circ\text{C}$ is worthless if packaged in an organic polymer that degrades or permits water vapor to attack the unpassivated junctions. For its landmark 900-series silicon transistors, TI instituted true hermetic metal packaging: a Kovar header with compression glass-to-metal seals mated to a deep-drawn nickel-plated Kovar can. Furthermore, because silicon crystals and eutectic contacts can easily withstand extreme heat, assemblies underwent an aggressive $200^\circ\text{C}$ high-vacuum bakeout—a temperature that would destroy a germanium transistor—to completely desorb chemisorbed moisture before being backfilled with ultra-dry nitrogen and resistance-welded into an impenetrable hermetic capsule.

## 1. High-Temperature Vacuum Bakeout: Silicon's 200°C Thermal Advantage

Thermal kinetics during pre-seal bakeout dictate the ultimate purity of the encapsulated cavity:
1. The Thermodynamics of Water Desorption:
Water vapor chemisorbs onto metal surfaces, glass eyelets, and silicon oxides with activation energies ranging from $E_{\text{desorp}} = 0.8\text{ to }1.2\ \text{eV}$. At ambient room temperature, or even under vacuum at $50^\circ\text{C}$, water molecules remain tenaciously bonded in multi-molecular layers:
* The Germanium Limitation ($85^\circ\text{C}$): Germanium devices soldered with soft lead-tin or bonded with low-melting eutectics could not be baked above $85\text{ to }100^\circ\text{C}$ without risk of thermal creep, solder liquefaction, or dopant smearing. Consequently, germanium cans always sealed in residual moisture that condensed during cold operation.
* Silicon’s High-Temperature Immunity ($200^\circ\text{C}$): Silicon melts at $1414^\circ\text{C}$, the gold-gallium base alloy solidifies at $363^\circ\text{C}$, and the silicone potting grease tolerates $> 200^\circ\text{C}$. This allowed TI to bake headers at $200^\circ\text{C}$ to $225^\circ\text{C}$ under high vacuum ($P < 10^{-4}\ \text{Torr}$) for several hours.
2. Purging the Internal Cavity:
At $200^\circ\text{C}$, thermal energy ($k_B T$) drastically lowers the residence time of adsorbed water molecules according to the Frenkel equation. Desorption rates accelerate by a factor of over $10^4$ compared to $85^\circ\text{C}$. Volatile organic solvents, trapped rinsing alcohols, and atmospheric gases are pumped out, leaving a bone-dry cavity with residual moisture content below $5\ \text{ppm}$.

## 2. Real Diagram: Vacuum Bake Chamber, Nitrogen Backfill, and Projection Weld

## 3. Projection Resistance Welding and Hermeticity Qualification

Sealing the can requires extreme localized heat without transferring thermal energy into the delicate crystal:
1. Projection Resistance Welding Mechanics:
Conventional flux-core solder or torch braze sealing releases volatile acidic fluxes and metallic fumes that permanently poison semiconductor surfaces. TI implemented projection resistance welding:
* Flange Ring Geometry: The drawn Kovar can features a circular embossed projection ridge along its mounting lip that concentrates mechanical force against the flat header flange.
* Microsecond Discharge Pulse: Clamping electrodes apply high compressive force while delivering a massive electrical pulse ($I \approx 2000\ \text{A}$ at low voltage for $10\ \text{milliseconds}$).
* Localized Solid-State Forging: Current crowding melts the embossed projection instantly, forging a continuous metallurgical grain boundary between can and header. The entire thermal pulse is so brief that temperature rise in the internal cavity is undetectable ($< 10^\circ\text{C}$).
2. Inert Gas Atmosphere:
Welding occurs directly inside a dry glove box chamber backfilled with $90\%\ \text{N}_2$ and $10\%\ \text{He}$ tracer gas at atmospheric pressure. The dew point of this gas stream is maintained below $-65^\circ\text{C}$, ensuring zero moisture is locked inside the sealed envelope.
3. Helium Leak Rate Qualification:
Finished cans are placed in a vacuum test vessel connected to a mass spectrometer tuned to detect helium ($M = 4$):
* An imperceptible micro-crack or porosity in the glass-to-metal seal or weld seam releases helium tracer gas.
* Every unit must exhibit a measured leak rate $Q_{\text{leak}} \le 1 \times 10^{-8}\ \text{atm}\cdot\text{cm}^3/\text{s}$.
* At this leak rate, it would require over 100 years for atmospheric moisture to diffuse into the can, guaranteeing permanent reliability in avionics and military applications.

## Hermetically Seal Can's Place in the Process Lineage

Hermetically sealing the can is step thirty-four of this project's 1954 silicon grown-junction transistor series — following chemical cleaning and silicone passivation, and preceding the final high-temperature qualification test. It encapsulates the fragile semiconductor matchstick inside an impermeable metal-and-glass vault, permanently locking in the pristine surface conditions established in earlier steps. Step thirty-five, final test and package, subjects the completed hermetic transistors to full electrical screening at both $25^\circ\text{C}$ and $150^\circ\text{C}$ to classify parameters and prove the silicon device's unprecedented thermal mastery.