silicon-on-insulator (soi) wafer

**Silicon-on-Insulator (SOI) Wafer** is a **specialized substrate consisting of a thin layer of crystalline silicon on top of a buried oxide (BOX) layer** — providing complete dielectric isolation between devices and the substrate, eliminating latchup and dramatically reducing parasitic capacitance. **What Is an SOI Wafer?** - **Structure**: Three layers: Device Si (top) | BOX (SiO₂, 10-400 nm) | Handle Si (bottom). - **Types**: - **FD-SOI** (Fully Depleted): Ultra-thin device layer (< 10 nm). Used in 22nm FD-SOI (GlobalFoundries, Samsung). - **PD-SOI** (Partially Depleted): Thicker device layer (50-100 nm). Used by IBM/AMD historically. - **Fabrication**: Bonded SOI (Smart Cut™) or SIMOX. **Why It Matters** - **No Latchup**: Complete oxide isolation eliminates all parasitic thyristor paths. - **Low Capacitance**: BOX layer reduces junction capacitance by 50-70% -> faster switching. - **Body Biasing**: FD-SOI enables back-gate body biasing for dynamic power/performance control. **SOI Wafers** are **silicon on a pedestal** — lifting transistors above the substrate on an insulating platform for superior isolation and performance.