Silicon Gate 1967 Deposit Polysilicon Gate Thermal Budget

# Step 2 — Deposit Polysilicon Instead of Metal, Because the Gate Must Survive What Comes Next: The Thermal Budget Inversion That Ruled Out Aluminum

## 1. Why the Gate Must Be Made of Silicon to Survive What Follows

Inverting the masking sequence in Step 1 created an immediate materials crisis: if the gate is patterned before the source and drain are formed, it must sit on the wafer through the high-temperature diffusion and anneal that drives dopant into the silicon, and aluminum cannot survive that thermal budget. In the 1962 metal-gate process, aluminum was evaporated as the very last step precisely because aluminum melts at 660 °C and forms an aluminum-silicon eutectic at 577 °C, whereas driving in boron or phosphorus dopants to form p-n junctions requires furnace temperatures between 950 °C and 1050 °C. Exposing an aluminum gate to a 1000 °C diffusion furnace causes it to melt, spike destructively through the hundred-nanometer gate oxide, and short directly to the substrate. To make the self-aligned gate work, the gate conductor had to be replaced with a refractory material that shares silicon's own thermal stability: polycrystalline silicon (polysilicon), deposited via silane pyrolysis ($SiH_4 \to Si + 2H_2$), which remains solid and stable up to silicon's melting point of 1414 °C.

$$T_{\text{eutectic,Al-Si}} = 577\ ^\circ\text{C} < T_{\text{melt,Al}} = 660\ ^\circ\text{C} \ll T_{\text{diffusion}} \approx 1000\ ^\circ\text{C} \ll T_{\text{melt,poly-Si}} = 1414\ ^\circ\text{C}$$

where $T_{\text{diffusion}}$ is the indispensable thermal window required to diffuse donor or acceptor impurities into single-crystal silicon and activate the lattice electrically. Because polysilicon's melting temperature $T_{\text{melt,poly-Si}}$ exceeds the diffusion temperature by more than 400 °C, the polysilicon gate withstands the subsequent high-temperature furnace step without melting, decomposing, or spiking through the underlying gate oxide.

Thermal Budget: Aluminum Destroys the Oxide, Polysilicon Survives behavior of candidate gate materials at 1000 °C source/drain diffusion ALUMINUM GATE AT 1000 °C Single-crystal silicon wafer Gate SiO2 Melts at 660 °C Eutectic spikes into channel DISASTROUS FAILURE Gate oxide punctured, channel shorted POLYSILICON GATE AT 1000 °C Single-crystal silicon wafer Gate SiO2 Solid to 1414 °C Pristine, coherent interface Zero spiking through oxide COMPLETELY STABLE Survives 1000 °C dopant drive-in unscathed Teutectic,Al-Si = 577 °C < Tmelt,Al = 660 °C << Tdiffusion ≈ 1000 °C << Tmelt,poly-Si = 1414 °C polysilicon shifts the gate thermal limit far above the dopant diffusion furnace temperature

## 2. Real Diagram: Chemical Vapor Deposition and Thermal Compatibility

The deposition of polycrystalline silicon directly onto amorphous silicon dioxide establishes a clean, high-temperature gate electrode without chemical attack on the delicate oxide layer beneath it.

LPCVD Polysilicon Deposition and Grain Structure silane pyrolysis deposits refractory polycrystalline silicon over amorphous gate oxide CHEMICAL VAPOR DEPOSITION: SiH4 (g) → Si (s) + 2H2 (g) at 600–650 °C silane gas decomposes uniformly across wafer surface in low-pressure vacuum furnace Polycrystalline Silicon Layer (Randomly Oriented Crystal Grains) Thermally Grown Silicon Dioxide (Gate Dielectric, SiO2 ~100 nm) Monocrystalline Silicon Substrate ([100] Lattice Orientation) ✓ Identical Thermal Expansion: Zero differential thermal stress between gate and substrate ✓ Dual Role: Conducts electrical gate bias while shielding the underlying channel from dopant

## 3. The Materials Consequence of Inverting the Process Order

The 1962 series built its transistors with an aluminum gate because aluminum was an established conductor in planar bipolar manufacturing, cheap to evaporate, and highly conductive. But 1962's process was constrained by an ironclad rule: aluminum could only be deposited after all high-temperature furnace operations were finished. Depositing aluminum at the end protected it from the 1000 °C diffusion furnace, but in return forced the gate to be aligned to pre-existing source and drain diffusions using a separate, error-prone photolithographic mask—creating the parasitic overlap capacitance that crippled switching speed.

Step 1 inverted that order to eliminate the alignment error, but this instantly made aluminum unusable. Depositing the gate *before* the source and drain meant the gate conductor had to withstand the full thermal budget of the dopant drive-in furnace. Replacing aluminum with polysilicon solved this material barrier completely. Because polysilicon is chemically silicon itself, its melting point (1414 °C) easily exceeds the 1000 °C diffusion furnace. Furthermore, because it matches the thermal expansion coefficient of the silicon wafer, thermal cycling does not induce interfacial shear stress or peel the thin gate oxide.

Finally, polysilicon offered an unexpected operational advantage: when the wafer entered the diffusion furnace to dope the source and drain regions, the unmasked polysilicon gate absorbed the same donor or acceptor dopants simultaneously. What was deposited as an undoped, high-resistivity silicon film emerged from the furnace as heavily doped, highly conductive degeneate silicon—providing both low gate resistance and an automatically self-aligned structure in a single thermal step.

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