Silicon Gate 1967 Diffuse Source Drain Self Aligned Mask

# Step 4 — Diffuse Source and Drain, Using the Gate Itself as the Mask: The Self-Aligned Diffusion That Resolves 1962's Alignment Problem

## 1. Why the Gate Conductor Is the Best Dopant Mask Ever Conceived

When the wafer enters the 1000 °C diffusion furnace, the patterned polysilicon gate performs two completely different engineering functions at the exact same physical instant: it acts as an impermeable diffusion mask that shadows the underlying channel from incoming dopant atoms, while simultaneously defining the exact geometric boundary where the source and drain junctions begin. In 1962's metal-gate process, the source and drain regions were diffused first through openings in thick silicon dioxide, and the metal gate had to be positioned afterward with a separate photolithographic alignment—a sequence that made overlap between the gate and the diffusions an uncontrolled variable dependent on mechanical tool alignment tolerance $\Delta_{\text{align}}$. In this step, no separate mask is used to register the gate to the diffusions. Instead, gaseous dopant (such as phosphorus or boron) impinges uniformly across the wafer surface: wherever the polysilicon gate stands, dopant cannot reach the channel; wherever the polysilicon was cleared in Step 3, dopant diffuses directly into the silicon substrate to form heavily doped, low-resistance source and drain electrodes.

$$L_{\text{overlap}} = x_{\text{lateral}} \approx 0.75\, x_j \ll L_{\text{overlap,1962}} = \Delta_{\text{align}} + x_{\text{lateral}}$$

where $x_j$ is the vertical junction depth determined by the diffusion time and temperature ($x_j = 2\sqrt{D t \ln(C_s/C_B)}$), and $x_{\text{lateral}}$ is the small, unavoidable sideways diffusion of dopant beneath the gate's physical edges. Because the gate's edge itself defined where the dopant entered the silicon, the alignment error term $\Delta_{\text{align}}$ that forced 1962 to oversize its gate is completely eliminated from the physical structure. The source and drain are self-aligned to the gate by construction.

Self-Aligned Diffusion: The Gate Shadows the Channel 1000 °C dopant flux enters substrate adjacent to gate and heavily dopes the gate itself DOPANT FLUX IN 1000 °C FURNACE (Phosphorus / Boron Vapor) Monocrystalline Silicon Substrate (Protected Channel Beneath Gate) Source Region (n+ / p+) Drain Region (n+ / p+) Gate Oxide (100 nm) Polysilicon Gate Absorbs Dopant → Becomes Degenerate Conductor xlat xlat Lchannel ≈ Wgate - 2xlateral ✓ Dual Action: Polysilicon blocks dopants from the channel while self-doping into a low-resistance gate ✓ Automatic Coincidence: Junction boundaries align precisely to gate edges without photolithographic alignment

## 2. Real Diagram: Collapse of Parasitic Overlap Capacitance

By replacing external mask registration with physical shadowing, the parasitic overlap length drops from a tool-limited tolerance ($\Delta_{\text{align}} \sim 2\text{--}3\ \mu\text{m}$) to microscopic thermal diffusion ($x_{\text{lateral}} \sim 0.2\ \mu\text{m}$).

Parasitic Overlap Geometry: 1962 Metal Gate vs. 1967 Self-Aligned Gate the structural source of Miller capacitance is reduced by nearly an order of magnitude 1962 METAL GATE (ALUMINUM) Source Drain Al Gate Loverlap = Δalign + xlateral ≈ 2.5 µm Massive parasitic overlap capacitance (Cgd) 1967 SILICON GATE (SELF-ALIGNED) Source Drain Poly-Si Gate Loverlap ≈ xlateral ≈ 0.25 µm Δalign term is entirely removed (10× lower Cgd) Miller Capacitance Formula: Coverlap = (εox / tox) · W · Loverlap Shrinking Loverlap from 2.5 µm to 0.25 µm directly divides feedback capacitance by 10×

## 3. Resolving the Central Bottleneck of the 1962 MOSFET Lineage

In the 1962 MOSFET lineage, the gate-to-drain overlap capacitance ($C_{\text{gd}}$) was the single most damaging parasitics in the device. In an inverting logic stage, the Miller effect multiplies this capacitance by the voltage gain of the gate:

$$C_{\text{in,effective}} = C_{\text{gs}} + (1 + |A_v|) C_{\text{gd}}$$

When $|A_v| \approx 5\text{--}10$, an overlap of even 2 µm caused $C_{\text{gd}}$ to completely dominate total input capacitance, slowing down circuit switching and limiting MOS logic to a fraction of bipolar switching speeds.

Step 4 resolves that bottleneck by eliminating its physical cause:
1. Perfect Coincidence: Because the gate conductor blocks dopant during diffusion, the source and drain regions are formed in immediate, exact contact with the gate edge. No lithographic misregistration can shift them apart.
2. Deterministic Overlap: The only remaining overlap is the physical sideways diffusion ($x_{\text{lateral}}$) governed by thermal kinetics, which is predictable, uniform across the wafer, and an order of magnitude smaller than optical alignment tolerance.
3. Simultaneous Gate Degeneration: The same dopant flux that creates the active source and drain areas penetrates the polysilicon gate, transforming the undoped polycrystalline silicon into a degenerate, highly conductive gate conductor without requiring a separate doping operation.

This single operation converts MOS technology from an experimental, speed-limited alternative into a high-density, high-speed digital logic platform.

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