simd instructions
**SIMD / Vectorization** — executing a Single Instruction on Multiple Data elements simultaneously using wide vector registers, achieving 4–16x speedup on data-parallel operations without multiple cores.
**How SIMD Works**
```
Scalar (1 at a time): SIMD (4 at a time):
a[0] = b[0] + c[0] a[0..3] = b[0..3] + c[0..3]
a[1] = b[1] + c[1] (single instruction!)
a[2] = b[2] + c[2]
a[3] = b[3] + c[3]
4 instructions 1 instruction
```
**x86 SIMD Evolution**
- **SSE** (1999): 128-bit registers → 4× float32 or 2× float64
- **AVX** (2011): 256-bit registers → 8× float32
- **AVX-512** (2017): 512-bit registers → 16× float32
- **AMX** (2023): Matrix extensions for AI inference on CPU
**ARM SIMD**
- **NEON**: 128-bit. Available on all modern ARM (phones, Apple Silicon)
- **SVE/SVE2**: Scalable Vector Extension. Variable-width (128–2048 bit). Used in ARM server CPUs
**Auto-Vectorization**
- Modern compilers (GCC, Clang, MSVC) automatically vectorize simple loops
- Flags: `-O2 -march=native` (GCC/Clang)
- Limitations: Complex control flow, data dependencies, non-contiguous access patterns prevent auto-vectorization
**Manual SIMD**
- Intrinsics: `__m256 result = _mm256_add_ps(a, b);`
- Used in performance-critical libraries (NumPy, OpenBLAS, FFmpeg)
**SIMD** is free parallelism within a single core — essential for high-performance numeric computation, media processing, and AI inference on CPUs.