simd intrinsics
**SIMD Intrinsics** are **low-level C/C++ functions that map directly to SIMD (Single Instruction Multiple Data) CPU instructions** — bypassing the compiler to explicitly exploit vector registers for processing 4, 8, 16, or 32 data elements per instruction.
**SIMD Evolution on x86**
| Extension | Register Width | Float/Int Elements | Year |
|-----------|--------------|-------------------|------|
| SSE2 | 128-bit (XMM) | 4 float / 2 double | 2001 |
| AVX | 256-bit (YMM) | 8 float / 4 double | 2011 |
| AVX2 | 256-bit + integer | 8 int32, 16 int16 | 2013 |
| AVX-512 | 512-bit (ZMM) | 16 float, 8 double | 2017 |
| AMX | 2D tile registers | Matrix multiply | 2021 |
**Example: AVX2 Vectorized Addition**
```c
#include
void add_arrays(float* a, float* b, float* c, int n) {
for (int i = 0; i < n; i += 8) {
__m256 va = _mm256_loadu_ps(a + i); // Load 8 floats
__m256 vb = _mm256_loadu_ps(b + i);
__m256 vc = _mm256_add_ps(va, vb); // Add 8 pairs in parallel
_mm256_storeu_ps(c + i, vc); // Store 8 results
}
}
```
**Key Intrinsic Categories**
- **Load/Store**: `_mm256_load_ps`, `_mm256_loadu_ps` (unaligned).
- **Arithmetic**: `_mm256_add_ps`, `_mm256_mul_ps`, `_mm256_fmadd_ps` (FMA).
- **Compare**: `_mm256_cmp_ps` → mask for conditional operations.
- **Shuffle/Permute**: `_mm256_permute_ps` — rearrange elements within vector.
- **Masked (AVX-512)**: `_mm512_mask_add_ps` — lane-selective operations.
**FMA (Fused Multiply-Add)**
- `_mm256_fmadd_ps(a, b, c)` = a×b + c in single instruction.
- 2x throughput vs. separate mul+add.
- Key for GEMM, dot products, convolution.
**When to Use Intrinsics vs. Auto-Vectorization**
- Compiler auto-vec: Often sufficient for simple loops.
- Intrinsics: When compiler fails (complex control flow, precision requirements, special shuffles).
- Profile first: Ensure vectorization is the actual bottleneck.
SIMD intrinsics are **the highest-performance path for compute-intensive loops** — critical path optimization in media codecs, ML inference engines, database scans, and scientific simulations routinely requires explicit vectorization to approach peak hardware throughput.