simultaneous switching noise (ssn)

**Simultaneous Switching Noise (SSN)** is the electrical noise generated when **many I/O drivers or internal circuits switch at the same time**, causing large transient currents through the parasitic inductance and resistance of power and ground paths. SSN is a superset of ground bounce that encompasses noise on both power (VDD) and ground (VSS) networks. **The Physics of SSN** - Each switching output draws a pulse of current from VDD (when switching low-to-high) or pushes current into VSS (when switching high-to-low). - When $N$ outputs switch simultaneously, the aggregate current change is approximately $N \times dI/dt$. - This current flows through the shared inductance ($L$) of the package and on-die power/ground networks, creating noise voltage: $V_{noise} = L \cdot N \cdot \frac{dI}{dt}$. **SSN Components** - **Power Bounce (VDD Droop)**: When many outputs switch high, they draw current from VDD simultaneously → VDD droops below nominal. - **Ground Bounce (VSS Rise)**: When many outputs switch low, they push current through VSS → VSS rises above true ground. - **Combined Effect**: The effective voltage swing seen by circuits is reduced: $V_{effective} = (VDD - droop) - (VSS + bounce)$. **Impact on Chip Performance** - **I/O Signal Integrity**: Non-switching outputs may glitch — a quiet LOW output referenced to a bounced ground appears HIGH. - **Core Logic Errors**: Internal circuits referenced to noisy power rails may see reduced noise margins, causing setup/hold violations. - **Jitter on Clocks**: SSN on clock distribution causes timing uncertainty. - **Analog Interference**: ADC accuracy, PLL stability, and reference voltage quality all degrade with SSN. **SSN Analysis** - **Worst-Case Pattern**: Identify the switching pattern that maximizes simultaneous switching — typically all outputs in a bank switching in the same direction at the same clock edge. - **Package Model**: Include accurate package parasitics — bond wire/bump inductance, plane capacitance, mutual inductance between adjacent pins. - **Frequency Domain**: Analyze the power delivery network impedance — SSN is worst at frequencies where the PDN impedance is highest (typically near the package resonance, 100 MHz–1 GHz). **SSN Mitigation** - **Reduce Simultaneous Switching**: Stagger output enables, use multiple clock phases, limit the number of outputs per power/ground group. - **Increase Power/Ground Connections**: More pins, bumps, or balls dedicated to power and ground — reduces shared inductance. - **On-Die Decoupling**: Decaps supply local charge during switching transients. - **Controlled Slew Rate**: Limit driver edge rates — slower transitions reduce $dI/dt$ at the cost of speed. - **Separated Power Domains**: Isolate noisy I/O banks from quiet I/O and core logic. - **SSO Guidelines**: Follow package SSO limits — the maximum number of simultaneously switching outputs per power/ground pair. SSN is the **combined power and ground noise challenge** of modern IC design — managing it requires holistic co-design of the chip I/O, package, and power delivery network.