Single Event Latchup

Single-event latchup (SEL) is what happens when a single heavy ion or high-energy proton strikes a CMOS chip and deposits enough charge to trigger the same parasitic pnpn thyristor structure that causes ordinary electrical latch-up, except here nothing electrical had to go wrong first — the particle itself is the trigger. The result is a low-impedance short between the power rail and ground that does not clear on its own the way a single-event upset's bit flip does; current keeps flowing at many times the chip's normal draw until something cuts the power, and if that does not happen fast enough the localized heating can physically destroy the device.

Heavy ion or proton strike
deposits charge along its track
Parasitic pnpn thyristor triggers
same structure as ordinary latch-up
Sustained low-impedance Vdd-to-ground path
current stays high, doesn't self-clear
Only fixed by removing power
Caught fast
power-cycle, device recovers
Caught too late
thermal damage, device dies

It is fundamentally different from the bit-flip failures people usually mean by "radiation effects." A single-event upset just flips one memory bit and the system corrects or rewrites it; SEL is a sustained hardware condition that persists at full current draw for as long as power stays applied, which is why a rad-hard power system needs its own current-limiting or current-sensing circuitry specifically to detect an SEL event and cut power within milliseconds, well before the strike has a chance to burn out a metal line or melt a junction.

One Particle, a Current That Won't Quit a strike through the parasitic pnpn turns on a thyristor that stays on parasitic pnpn in bulk CMOS P+ (Vdd contact) N-well N+ (GND contact) P-substrate ion track triggers the thyristor supply current vs. time strike sustained high current — no self-clear LET threshold, current limiting, and response time are the three numbers an SEL test report actually has to deliver

Qualification happens at a particle accelerator, not on a bench. Rad-hard and aerospace parts get SEL-tested by exposing them to a heavy-ion beam at facilities like the Texas A&M Cyclotron Institute or Lawrence Berkeley National Lab's 88-Inch Cyclotron, sweeping the linear energy transfer (LET, measured in MeV·cm²/mg) of the beam upward to find the threshold LET at which SEL events start occurring, following test methods standardized in JEDEC's JESD57; a part with no SEL observed up to a high LET threshold is rated far more suitable for a satellite or deep-space mission than one that latches up at a low threshold.

This is a large part of why rad-hard parts exist as a separate product category at all. Suppliers like Microchip (through its former Microsemi/Actel rad-hard FPGA lines), BAE Systems, and Honeywell Aerospace build process variants and layout techniques — guard rings, retrograde wells, silicon-on-insulator isolation — specifically to push the SEL threshold LET high enough that a part can survive the galactic cosmic ray and solar particle environment a satellite or deep-space probe actually flies through, at a cost and performance penalty that a terrestrial chip never has to pay.

Read SEL through a *does-it-self-clear* lens rather than a *does-it-glitch* lens — a single-event upset is a transient the system can design around, but SEL is a sustained electrical fault that will keep drawing damaging current for as long as power stays on, which is why the only real fix at the system level is detecting it and cutting power faster than the heat can build.

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