Source

Source and drain are the two terminals a transistor's current actually flows between — heavily doped regions carved into the substrate on either side of the gate, each a small reservoir of free carriers waiting for the channel underneath the gate to connect them. The source supplies carriers into the channel; the drain collects them on the far side. Which one is which depends on which way current is flowing, not on any physical difference between them — in most circuit configurations the two are built identically and only earn their separate names from how they're wired up.

Source and drain are made the same way — heavily doped pockets of silicon with the opposite doping type from the surrounding substrate. In an NMOS transistor sitting in p-type substrate, source and drain are both n+ regions: doped so heavily with donor atoms that they behave almost like a metal, happy to supply or absorb electrons with very little resistance. The gate sits directly between them, and the thin strip of substrate underneath the gate — the channel region — is the only part of the structure whose conductivity actually changes when the gate switches. Source and drain themselves are always conductive; what changes is whether a path exists between them.

Which terminal is the source and which is the drain is a matter of current direction, not geometry. By convention, the source is the terminal that supplies the carriers that do the conducting — electrons for an NMOS transistor, holes for a PMOS transistor — and the drain is the terminal that receives them. In a simple inverter or logic gate, this assignment is fixed by the circuit wiring and stays constant. But in some circuits, such as a pass-transistor used to route a signal in either direction, the same two terminals can swap roles from one moment to the next depending on which side currently sits at the higher or lower voltage. The industry still gives them separate names and separate symbols on a schematic, but at the device level they are interchangeable terminals with no built-in asymmetry forcing one role or the other.

The drain side carries almost all of a transistor's electric-field stress, which is why real source/drain regions aren't simple uniform blocks. When a transistor switches, the drain end of the channel sees the largest voltage drop and the strongest electric field, and that field can accelerate carriers enough to generate secondary carriers through impact ionization — a reliability concern called hot-carrier injection that gradually degrades the transistor over its lifetime. Advanced source/drain designs counter this with graded doping profiles near the drain edge (lightly-doped drain, or LDD, extensions) that spread the voltage drop over a longer distance and reduce the peak field, trading a small amount of resistance for a large improvement in long-term reliability.

Modern source/drain regions are also where a huge amount of strain engineering happens. Starting around the 90 nm node, foundries began replacing the source and drain silicon with a different crystal — silicon-germanium for PMOS, silicon-carbon for NMOS — grown epitaxially to physically squeeze or stretch the channel sitting between them. That mechanical strain distorts the silicon's crystal lattice just enough to make it easier for carriers to move through the channel, directly boosting switching speed without needing to shrink anything further. This is one of several "more than scaling" tricks — improving transistor performance at a fixed geometry rather than through pure dimensional shrink — that kept Moore's Law-era performance gains coming even as pure lithographic scaling slowed down.

At advanced nodes, source and drain have become one of the hardest parts of the transistor to manufacture well. As gate lengths shrank, the distance available for source and drain to connect to the channel shrank with them, and the contact resistance of simply connecting a metal wire to these tiny doped regions became a bottleneck in its own right — sometimes a bigger speed limiter than the channel itself. FinFET and gate-all-around transistors wrap source and drain around a vertical fin or horizontal nanosheet rather than laying them flat, and foundries now routinely use selective epitaxial growth to build source/drain regions up and out from the fin in custom shapes, maximizing the contact area available for the metal connections stacked on top.