sram bitcell scaling

```svg ``` **SRAM Bitcell Scaling** — the challenge of shrinking the basic SRAM memory cell at each technology node, often considered the most demanding layout challenge and the benchmark for process capability. **6T SRAM Cell** - 6 transistors per bit: 2 pull-up PMOS + 2 pull-down NMOS + 2 access NMOS - Cross-coupled inverters store one bit (0 or 1) - Access transistors controlled by word line **Why SRAM Is the Benchmark** - Contains the smallest transistors at minimum pitch in every dimension - Tests the process at its absolute limits - First structure to work (or fail) at a new node - SRAM yield is a leading indicator of process maturity **Bitcell Area Scaling** | Node | Bitcell Area | Density | |---|---|---| | 14nm | 0.059 μm² | ~17 Mbit/mm² | | 7nm | 0.027 μm² | ~37 Mbit/mm² | | 5nm | 0.021 μm² | ~48 Mbit/mm² | | 3nm | 0.0199 μm² | ~50 Mbit/mm² | **Scaling Challenges** - Read stability: Access transistor must not flip the cell during read - Write-ability: Must be able to overwrite the cross-coupled inverters - Leakage: 6 transistors × billions of cells = significant standby power - Variability: Random dopant fluctuation (RDF) causes $V_{th}$ mismatch **Alternatives** - 8T SRAM: Separate read port eliminates read-disturb. ~30% larger but more robust - Gain cell (2T/3T): Smaller but needs refresh. Research stage **SRAM bitcell area** is the most commonly cited metric for comparing process technologies — it's the truest measure of a node's capability.