SRAM Cell Ratio
SRAM cell ratio and beta ratio are the two transistor-width ratios inside a 6T bitcell that decide whether it can be written at all and whether it can be read without accidentally flipping itself — and the two ratios pull in opposite directions, so sizing a bitcell is a direct tug-of-war between them. At a high level, the two contests look like this:
A few things are worth knowing about why these two ratios, not raw transistor sizes, are the number designers actually track:
Beta ratio protects the bit during a read. Reading a 6T cell means turning on the pass-gate and letting the bitline, precharged high, sit directly on top of the node storing a 0 — if the pull-down transistor is too weak relative to the pass-gate, that bitline voltage can pull the internal node up far enough to flip the cell before the sense amplifier ever gets a clean signal. Beta ratio (pull-down width over pass-gate width, typically sized above 1 for logic SRAM) is exactly the margin against that failure, usually quantified as the static noise margin (SNM) on the cell's butterfly curve.
Cell ratio does the opposite job during a write. Writing a 1 into that same cell means the pass-gate and the write driver have to overpower the pull-up transistor holding the old value — so a strong pass-gate relative to the pull-up (high cell ratio, pass-gate width over pull-up width) is what makes a write succeed quickly. That is precisely the transistor relationship beta ratio is trying to keep weak on the read side, which is why the two specs are quoted together: push beta ratio up for read stability and the same pass-gate looks relatively weaker for writes, so cell ratio has to be managed independently rather than inferred from beta ratio.
FinFET and GAA scaling made this a quantized, not continuous, sizing problem. In a planar or early-FinFET process a designer could dial transistor width almost continuously; once fin width (and later nanosheet width) is fixed by the process, usable widths only come in integer multiples of one fin or one sheet, so beta ratio and cell ratio collapse onto a small set of discrete values (1:1, 2:1, 3:2, ...) instead of a smooth curve — a known pressure point referenced directly from the FinFET-era design-history material, where the industry had to accept coarser bitcell stability margins than idealized sizing would have chosen, specifically because fin quantization removed the fine-grained width control planar CMOS used to allow.
Read beta ratio and cell ratio as the same transistor playing two roles that want opposite strength: every SRAM bitcell sizing decision is really a trade between how hard it is to disturb a bit during a read and how easy it is to overwrite that same bit during a write, and the smaller the process node gets, the fewer discrete sizing choices are left to balance that trade.