Stacked CMOS Image Sensor
# Stacked CMOS Image Sensor: Pixel-Logic Die Separation
A stacked CMOS image sensor splits the pixel array and the supporting logic circuitry onto two separate dies, each fabricated on a process optimized for its own job, then bonds the two together — the same divide-and-specialize strategy HBM uses to separate DRAM dies from a logic base die, applied here to separate light-sensing pixels from the signal-processing circuitry that reads them out. A conventional single-die image sensor has to fit both the photodiode array and all the readout, analog-to-digital conversion, and signal-processing circuitry onto one piece of silicon, built on one compromise process that can't be fully optimized for either job. Splitting those two functions onto separate dies — a pixel die built on a process tuned for photodiode performance and light sensitivity, and a logic die built on a process tuned for fast digital circuitry — lets each half use whichever process actually suits it, then joins the two through die-to-die bonding.
This separation directly increases how much of the pixel die's area can actually be devoted to light-sensing photodiodes, because none of the readout and processing circuitry that used to compete for space on the same die is there anymore — it's been moved entirely onto the separate logic die underneath. On a single-die sensor, every transistor needed for readout and processing takes up area that could otherwise be photodiode, directly limiting how much of each pixel's area can actually capture light — a real constraint as pixel sizes continue to shrink. Moving that circuitry to its own die frees up essentially the entire pixel die's area for photodiodes, and lets the logic die integrate considerably more processing capability than would ever fit alongside the pixels on a single shared die.
Freeing up logic-die area this way has enabled a progression toward genuinely more processing capability close to the sensor itself — some stacked sensor designs now integrate a third die for memory or additional compute, directly supporting faster readout and on-sensor image processing that a space-constrained single-die or even standard two-die design couldn't accommodate. This is the same underlying logic as HBM's base-die specialization applied one step further: once pixel and logic are already separated, adding yet another specialized die for memory or compute is a natural next step rather than a fundamentally new idea, since the stacking and bonding infrastructure to join multiple specialized dies is already part of the sensor's basic architecture.
HBM's base die separates DRAM-process storage from logic-process control circuitry for exactly the same underlying reason stacked image sensors separate pixel-process photodiodes from logic-process readout circuitry — process specialization through die stacking turns out to be a general strategy that recurs across completely different chip categories whenever a single compromise process can no longer serve two genuinely different circuit functions well.