standard cell design

**Standard Cell Design** — creating the fundamental logic building blocks (gates, flip-flops, buffers) that are tiled in rows to build digital chips, characterized for timing, power, and noise across all operating conditions. **What Standard Cells Are** - Fixed-height cells that snap to placement rows - Variable width depending on function and drive strength - Examples: INV, NAND2, NOR3, MUX2, DFF, SDFF, ICG, buffer - A typical library: 500–2000+ unique cells **Cell Design Process** 1. **Schematic**: Transistor-level circuit design. Optimize transistor sizing 2. **Layout**: Manual layout within cell boundary rules. Meet DRC, optimize for area, performance 3. **Extraction**: Extract parasitics from layout (R, C) 4. **Characterization**: SPICE simulate across all PVT corners → generate Liberty (.lib) timing models 5. **Verification**: DRC, LVS clean. Antenna clean. ERC clean **Characterization Data (Liberty .lib)** - Delay: f(input_slew, output_load) — 7×7 lookup table per arc - Setup/hold time: For sequential cells - Power: Switching, internal, leakage — per input pin transition - Noise: Output noise immunity curves **Cell Library Variants** - Track height: 7.5T (performance), 6T (density), 5T (ultra-dense). Tracks = number of metal routing tracks in cell height - Threshold voltage: HVT, SVT, LVT, ULVT versions of every cell **Standard cells** are the atoms of digital design — their quality directly determines the PPA (Power, Performance, Area) of every chip built with them.