standard cell library

**Standard Cell Library** — a collection of pre-designed, pre-characterized logic gates and flip-flops that serve as the building blocks for synthesized digital circuits. **What Libraries Contain** - **Logic cells**: AND, OR, NAND, NOR, XOR, MUX, buffers, inverters - **Sequential cells**: Flip-flops (DFF), latches, scan flip-flops - **Special cells**: Clock buffers, level shifters, isolation cells, always-on cells **Cell Variants (Drive Strengths)** - Each function available in multiple sizes (X1, X2, X4, X8...) - Larger cells: Faster but more area and power - Synthesis tools select optimal size for each instance **Characterization (Liberty .lib format)** - Timing: Setup, hold, propagation delay (lookup tables for input slew x output load) - Power: Dynamic (switching + internal) and leakage power - Multiple PVT corners (SS/TT/FF, voltage, temperature) **Multi-Vt Libraries** - **HVT (High Threshold)**: Slow but low leakage — for non-critical paths - **SVT (Standard)**: Balanced - **LVT (Low Threshold)**: Fast but high leakage — for timing-critical paths - **ULVT**: Fastest, highest leakage — sparingly used **Standard cell libraries** are provided by the foundry or third-party IP vendors and are specific to each process node.