State-Machine

A finite state machine is a circuit built from exactly two parts — a bank of flip-flops holding the machine's current state, and combinational logic that computes both the next state and the machine's outputs from that current state and whatever inputs are present — giving a chip a structured, deliberate way to behave differently depending on what's already happened, not just what's happening right now. "Finite" means the machine has a fixed, countable number of distinct states it can ever occupy; "state" means its entire behavior at any moment is completely determined by which one of those states it currently sits in, plus its current inputs. How a state machine actually computes its next state and its outputs, one clock cycle at a time, looks like this:

A few things are worth knowing about why separating "what state am I in" from "what should happen next" turns out to be such a powerful, widely reused way to structure digital control logic:

A state machine's defining property is that its entire future behavior depends only on its current state and current inputs, never on how it arrived at that state — a property that makes its behavior completely predictable and fully specifiable in advance, unlike logic that tries to track an unbounded, open-ended history of everything that's happened. Two different paths of inputs that happen to land the machine in the exact same state will, from that point forward, behave identically no matter how differently they got there, because the state itself is the only thing that matters going forward — the entire relevant history is compressed down into whichever single state the machine currently occupies. This is exactly why state machines are specified with a state diagram or a state transition table listing every state and every possible transition out of it: because the behavior truly is fully determined by current state and current input alone, that complete table is also a complete, exhaustive specification of everything the machine can ever do.

A Moore machine computes its outputs purely from the current state, while a Mealy machine computes outputs from both the current state and the current inputs together, and that single design choice has real, practical consequences for both timing behavior and how compact the resulting state diagram ends up. A Moore machine's output changes only when the state itself changes, at a clock edge, which means its outputs are inherently stable and glitch-free between clock edges — a useful property for driving signals that other logic depends on cleanly. A Mealy machine's output can change the instant an input changes, even without waiting for the next clock edge, which often lets the same overall behavior be expressed with fewer total states, since a single state can produce different outputs depending on which input is currently present, rather than needing a separate state for every output variation. Neither style is universally better — Moore machines are generally favored when output stability matters most, Mealy machines when minimizing state count or reacting to inputs without clock-edge delay matters more — and real designs choose deliberately between the two based on which tradeoff fits the specific application.

A state machine's hardware implementation splits cleanly into two separate logic blocks with genuinely different jobs, and keeping that separation clear is exactly what makes state machine design tractable rather than an undifferentiated mass of logic gates. The state register, a bank of flip-flops, does nothing but hold the current state value, one encoding per distinct state, and update to a new value on each clock edge. The next-state logic and output logic, both purely combinational with no memory of their own, compute what the next state should become and what the outputs should currently be, based entirely on reading the state register's current value and the circuit's current inputs. This clean separation — memory in one place, decision-making logic in another — is exactly the same fundamental architecture underlying every sequential circuit built from flip-flops plus combinational logic, with a state machine simply being that same pattern applied deliberately and explicitly to implement a specific, designed control behavior.

State machines are the standard tool for implementing control logic throughout a chip precisely because so much of what a chip needs to coordinate — bus protocols, peripheral interfaces, instruction decoding sequences — is naturally described as "do this specific thing while in this specific situation, then move to the next situation," exactly the structure a state diagram captures directly. A USB or SPI peripheral interface implementing its communication protocol, a memory controller sequencing through the specific steps needed to read or write a DRAM chip, and even the instruction decoder inside a simple processor core sequencing through fetch, decode, and execute phases are all naturally expressed as state machines, because each of these genuinely has a small number of distinct operational phases with well-defined rules for transitioning between them. This is exactly why state machine design remains one of the most fundamental, widely applicable skills in digital logic design, showing up identically whether the chip in question is an enormous, billion-transistor processor or the simplest possible peripheral controller.

Read a state machine as compressed history made explicit, not an arbitrary way to organize control logic: the current state alone fully captures everything about the past that matters for future behavior, the clean split between state-holding flip-flops and purely combinational next-state logic is what makes that behavior fully specifiable in a state diagram, and the choice between Moore's output stability and Mealy's often-more-compact encoding is a deliberate tradeoff every real state machine design has to make — which is exactly why this same pattern reappears throughout chip design wherever behavior genuinely depends on "what situation am I currently in," from the smallest peripheral controller to the sequencing logic inside a full processor core.