static timing analysis sta

**Static Timing Analysis (STA)** is the **exhaustive mathematical verification method that checks every timing path in a digital design against setup and hold constraints without requiring simulation vectors — computing the arrival time of data signals at every flip-flop input and comparing against the clock arrival time to determine whether the design meets timing at all specified operating conditions (process corners, voltages, temperatures, and functional modes)**. **Why STA Instead of Simulation** Dynamic timing verification (gate-level simulation) can only check the specific input patterns applied — it cannot prove that timing is met for all possible input combinations. STA is exhaustive: it traces every possible timing path through the combinational logic and verifies that the slowest path meets setup requirements and the fastest path meets hold requirements. This completeness makes STA the mandatory timing sign-off method for all digital designs. **Timing Path Anatomy** - **Launch Path**: Clock → source flip-flop clock pin → Q output through combinational logic to the data pin (D) of the destination flip-flop. - **Capture Path**: Clock → destination flip-flop clock pin. - **Setup Check**: Data arrival time at D must be earlier than clock arrival time at destination by the setup time (Tsetup). Slack = (clock arrival - Tsetup) - data arrival. Positive slack = timing met. - **Hold Check**: Data must be stable at D for at least Thold after the capturing clock edge. Slack = data arrival - (clock arrival + Thold). Positive slack = timing met. **Multi-Corner Multi-Mode (MCMM)** Timing must be verified across all combinations of: - **Corners**: Process (slow/typical/fast), Voltage (nominal/low/high), Temperature (hot/cold). Each corner produces a different set of cell delays. A typical sign-off checks 15-50 PVT corners. - **Modes**: Each functional mode (normal, sleep, test, low-power) has different clock frequencies, active domains, and constraints. Setup timing is most critical at the slow corner (worst-case delays). Hold timing is most critical at the fast corner (signals arrive too quickly). Both must pass simultaneously. **On-Chip Variation (OCV)** Cells on the same die can have different delays due to local process variation (random dopant fluctuation, line-edge roughness). STA models this with OCV derating — applying pessimistic derating factors (AOCV or POCV, based on path depth and distance) to ensure timing closure even with on-chip variation. **STA Sign-Off Criteria** - **Zero negative slack (TNS = 0, WNS ≥ 0)**: No timing violations on any path at any corner/mode. - **Clock uncertainty budget**: Allocated for jitter, OCV, and CTS implementation imperfections. - **SI-aware**: Crosstalk-induced delay effects (coupling capacitance between adjacent wires) are included in delay calculations. Static Timing Analysis is **the mathematical proof that the chip will work at speed** — the single most important verification step in physical design, without which no chip can tape out.