Stress-Liner

A stress liner is a deposited film engineered to transfer mechanical stress into nearby devices. In CMOS, silicon nitride liners are a familiar example. Film composition and deposition conditions can produce tensile or compressive intrinsic stress. The electrical purpose is to create a useful strain state in the transistor channel through the surrounding mechanical structure.

Film stress and channel stress are connected through device geometry. Gate height, spacer shape, isolation, contacts, and nearby patterns influence how a liner loads the channel. A blanket-film stress measurement is therefore one input to device engineering rather than a complete transistor specification. Local stress transfer is a three-dimensional mechanical problem.

Stress liner Conceptual comparison; not a manufacturing specification or scale drawing Film engineering Nitride composition + deposition Tensile or compressive stress Stress transfer Gate / spacers / isolation Layout-dependent channel strain Additional function Contact etch stop when designed Selectivity + reliability A film’s intrinsic stress and the channel’s final strain are related through the complete patterned structure.

Complementary devices can require different liner conditions. Tensile and compressive schemes are selected according to carrier type, crystal orientation, and the intended transport improvement. A dual-stress-liner process uses distinct film treatments in different device regions. Extra patterning and interfaces must be managed while preserving the intended mechanical effect.

A liner may also perform a process-control function. A contact etch stop layer helps protect underlying features during contact-hole etching. When the same film is stress engineered, etch selectivity and mechanical loading become coupled requirements. Meeting one does not guarantee that the other is satisfactory after later thermal and plasma steps.

Qualification links the film to electrical behavior across realistic layouts. Drive current, leakage, variability, and reliability are evaluated after the integrated process. Layout-dependent effects can require explicit device-model treatment. A useful stress liner is therefore a controlled element of transistor integration, with both mechanical and fabrication constraints.

Sources and further reading. [Thompson et al., A Logic Nanotechnology Featuring Strained-Silicon, 2004](https://doi.org/10.1109/LED.2004.825195); [Thompson et al., Uniaxial-Process-Induced Strained-Si, 2006](https://doi.org/10.1109/TED.2006.872088).

Read Stress liner as a process-engineered film that couples local mechanics to transistor performance and fabrication requirements.

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